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| INTEGRATED CIRCUITS DATA SHEET UDA1380 Stereo audio coder-decoder for MD, CD and MP3 Product specification 2002 Sep 16 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 CONTENTS 1 1.1 1.2 1.3 1.4 1.5 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 FEATURES General Multiple format data input interface Multiple format data output interface ADC front-end features DAC features APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Clock modes ADC analog front-end Decimation filter (ADC) Interpolation filter (DAC) Noise shaper FSDAC Headphone driver Digital and analog mixers (DAC) Application modes Power-on reset Power-down requirements Plop prevention Digital audio data input and output L3-BUS INTERFACE DESCRIPTION Introduction Device addressing Slave address Register addressing Data write mode Data read mode I2C-BUS INTERFACE DESCRIPTION Addressing WRITE cycle READ cycle REGISTER MAPPING Evaluation modes and clock settings I2S-bus input and output settings Power control settings Analog mixer settings Reserved Master volume control Mixer volume control Mode, bass boost and treble 2 22 23 24 25 11.11 11.12 11.13 11.14 11.15 11.16 11.17 12 13 14 15 16 17 18 19 20 21 21.1 21.2 21.3 21.4 21.5 11.9 11.10 UDA1380 Master mute, channel de-emphasis and mute Mixer, silence detector and oversampling settings Decimator volume control PGA settings and mute ADC settings AGC settings Restore L3 default values (software reset) Headphone driver and interpolation filter (read-out) Decimator read-out LIMITING VALUES HANDLING THERMAL CHARACTERISTICS QUALITY SPECIFICATION DC CHARACTERISTICS AC CHARACTERISTICS TIMING APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2002 Sep 16 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 1 1.1 FEATURES General UDA1380 * 2.4 to 3.6 V power supply * 5 V tolerant digital inputs (at 2.4 to 3.6 V power supply) * 24-bit data path for Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) * Selectable control via L3-bus microcontroller interface or I2C-bus interface; choice of 2 device addresses in L3-bus and I2C-bus mode Remark: This device does not have a static mode * Supports sample frequencies from 8 to 55 kHz for the ADC part, and 8 to 100 kHz for the DAC part. The ADC cannot support DVD audio (96 kHz audio), only Mini-Disc (MD), Compact-Disc (CD) and Moving Picture Experts Group Layer-3 Audio (MP3). For playback 8 to 100 kHz is specified. DVD playback is supported * Power management unit: - Separate power control for ADC, Automatic Volume Control (AVC), DAC, Phase Locked Loop (PLL) and headphone driver - Analog blocks like ADC and Programmable Gain Amplifier (PGA) have a block to power-down the bias circuits - When ADC and/or DAC are powered-down, also the clocks to these blocks are stopped to save power Remark: By default, when the IC is powered-up, the complete chip will be in the Power-down mode. * ADC part and DAC part can run at different frequencies, either system clock or Word Select PLL (WSPLL) * ADC and PGA plus integrated high-pass filter to cancel DC offset * The decimation filter is equipped with a digital Automatic Gain Control (AGC) * Mono microphone input with Low Noise Amplifier (LNA) of 29 dB fixed gain and Variable Gain Control (VGA) from 0 to 30 dB in steps of 2 dB * Integrated digital filter plus DAC * Separate single-ended line output and one stereo headphone output, capable of driving a 16 load. The headphone driver has a built-in short-circuit protection with status bits which can be read out from the L3-bus or I2C-bus interface * Digital silence detection in the interpolator (playback) with read-out status via L3-bus or I2C-bus interface * Easy application. 1.2 Multiple format data input interface * Slave BCK and WS signals * I2S-bus format * MSB-justified format compatible * LSB-justified format compatible. 1.3 Multiple format data output interface * Select option for digital output interface: either the decimator output (ADC signal) or the output signal of the digital mixer which is in the interpolator DSP * Selectable master or slave BCK and WS signals for digital ADC output Remark: SYSCLK must be applied in WSPLL mode and master mode * I2S-bus format * MSB-justified format compatible * LSB-justified format compatible. 1.4 ADC front-end features * ADC plus decimator can run at either WSPLL, regenerating the clock from WSI signal, or on SYSCLK * Stereo line input with PGA: gain range from 0 to 24 dB in steps of 3 dB * LNA with 29 dB fixed gain for mono microphone input, including VGA with gain from 0 to 30 dB in steps of 2 dB * Digital left and right independent volume control and mute from +24 to -63.5 dB in steps of 0.5 dB. 2002 Sep 16 3 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 1.5 DAC features UDA1380 The DAC part is equipped with a stereo line output and a headphone driver output. The headphone driver is capable of driving a 16 load. The headphone driver is also capable of driving a headphone without the need for external DC decoupling capacitors, since the headphone can be connected to a pin VREF(HP) on the chip. In addition, there is a built-in short-circuit protection for the headphone driver output which, in case of short-circuit, limits the current through the operational amplifiers and signals the event via its L3-bus or I2C-bus register. The UDA1380 also supports an application mode in which the coder-decoder itself is not running, but an analog signal, for instance coming from an FM tuner, can be controlled in gain, and applied to the output via the headphone driver and line outputs. The UDA1380 supports the I2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 18, 20 or 24 bits (LSB-justified 24 bits is only supported for the output interface). The UDA1380 has sound processing features in playback mode, de-emphasis, volume, mute, bass boost and treble which can be controlled by the L3-bus or I2C-bus interface. * DAC plus interpolator can run at either WSPLL (regenerating the clock from WSI) or at SYSCLK * Separate digital logarithmic volume control for left and right channels via L3-bus or I2C-bus from 0 to -78 dB in steps of 0.25 dB * Digital tone control, bass boost and treble via L3-bus or I2C-bus interface * Digital de-emphasis for sample frequencies of: 32, 44.1, 48 and 96 kHz via L3-bus or I2C-bus interface * Cosine roll-off soft mute function * Output signal polarity control via L3-bus or I2C-bus interface * Digital mixer for mixing ADC output signal and digital serial input signal, if they run at the same sampling frequency. 2 APPLICATIONS This audio coder-decoder is suitable for home and portable applications like MD, CD and MP3 players. 3 GENERAL DESCRIPTION The UDA1380 is a stereo audio coder-decoder, available in TSSOP32 (UDA1380TT) and HVQFN32 (UDA1380HN) packages. All functions and features are identical for both package versions. The term `UDA1380' in this document refers to both UDA1380TT and UDA1380HN, unless particularly specified. The front-end of the UDA1380 is equipped with a stereo line input, which has a PGA control, and a mono microphone input with an LNA and a VGA. The digital decimation filter is equipped with an AGC which can be used in case of voice-recording. 2002 Sep 16 4 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 4 QUICK REFERENCE DATA VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies VDDA(AD) VDDA(DA) VDDA(HP) VDDD IDDA(AD) ADC analog supply voltage DAC analog supply voltage headphone analog supply voltage digital supply voltage ADC analog supply current one ADC and microphone amplifier enabled; fs = 48 kHz two ADCs and PGA enabled; fs = 48 kHz 2.4 2.4 2.4 2.4 - - 3.0 3.0 3.0 3.0 4.5 7.0 3.3 1.0 3.4 0.1 0.9 0.1 10.0 5.0 6.0 1.0 9.0 8.8 13.0 10.0 13.0 23.0 12.0 3.6 3.6 3.6 3.6 - - - - - - - - - - - - - - - - - - - V V V V mA mA mA A mA A mA A mA mA mA A mA mA mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT all ADCs and PGAs power-down, but - AVC activated; fs = 48 kHz all ADCs, PGAs and LNA power-down; fs = 48 kHz IDDA(DA) IDDA(HP) IDDD DAC analog supply current headphone analog supply current digital supply current operating mode; fs = 48 kHz Power-down mode; fs = 48 kHz no signal applied (quiescent current) Power-down mode operating mode; fs = 48 kHz playback mode; fs = 48 kHz record mode; fs = 48 kHz Power-down mode; fs = 48 kHz IDD(tot) total supply current - - - - - - - - - playback mode (without headphone); - fs = 48 kHz playback mode (with headphone); no - signal; fs = 48 kHz record mode (audio); fs = 48 kHz record mode (speech); fs = 48 kHz record mode (audio and speech); fs = 48 kHz fully operating; fs = 48 kHz signal mix-in operating, using FSDAC, AVC (with headphone); no signal; fs = 48 kHz Power-down mode; fs = 48 kHz - - - - - - -40 2.0 - - +85 A C Tamb ambient temperature 2002 Sep 16 5 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 SYMBOL PARAMETER CONDITIONS MIN. - - - - - at 0 dBFS digital output; 2.2 k source impedance at 0 dB at -60 dB; A-weighted Vi = 0 V; A-weighted - - - - - at 0 dBFS digital input; note 1 at 0 dB at -60 dB; A-weighted at 0 dB at -60 dB; A-weighted code = 0; A-weighted code = 0; A-weighted - - - - - - - - - at 0 dB at -60 dB; A-weighted Vi = 0 V; A-weighted - - - TYP. -1 -85 -37 97 100 - -74 -25 85 70 UDA1380 MAX. - - - - - 35 - - - - - - - - - - - - - - - - UNIT Analog-to-digital converter (supply voltage 3.0 V) Do digital output level at 0 dB setting; Vi(rms) = 1.0 V at -1 dBFS at -60 dBFS; A-weighted Vi = 0 V; A-weighted dBFS dB dB dB dB (THD+N)/S48 total harmonic distortionplus-noise to signal ratio at fs = 48 kHz S/N48 cs Vi(rms) signal-to-noise ratio at fs = 48 kHz channel separation LNA input plus analog-to-digital converter (supply voltage 3.0 V) input voltage (RMS value) mV dB dB dB dB (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz S/N48 cs Vo(rms) signal-to-noise ratio at fs = 48 kHz channel separation Digital-to-analog converter (supply voltage 3.0 V) output voltage (RMS value) 0.9 -88 -40 -80 -37 100 97 90 V dB dB dB dB dB dB dB (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz (THD+N)/S96 total harmonic distortion-plus-noise to signal ratio at fs = 96 kHz S/N48 S/N96 cs Vi(rms) signal-to-noise ratio at fs = 48 kHz signal-to-noise ratio at fs = 96 kHz channel separation AVC (line input via ADC input; output on line output and headphone driver; supply voltage 3.0 V) input voltage (RMS value) 150 -80 -28 87 mV dB dB dB (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz S/N48 signal-to-noise ratio at fs = 48 kHz 2002 Sep 16 6 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 SYMBOL PARAMETER CONDITIONS at 0 dBFS digital input; RL = 16 at 0 dB; RL = 16 at 0 dB; RL = 5 k at -60 dB; A-weighted code = 0; A-weighted RL = 16 using pin VREF(HP); no DC decoupling capacitors; note 2 RL = 16 single-ended application with DC decoupling capacitors (100 F typical) RL = 32 single-ended application with DC decoupling capacitors (100 F typical) Power consumption (supply voltage 3.0 V; fs = 48 kHz) Ptot total power dissipation playback mode (without headphone) playback mode (with headphone) record mode (audio) record mode (speech) record mode (audio and speech) full operation Power-down mode Notes 1. The output voltage of the DAC is proportional to the DAC power supply voltage. 2. Channel separation performance is measured at the IC pin. 5 ORDERING INFORMATION TYPE NUMBER UDA1380TT UDA1380HN PACKAGE NAME TSSOP32 HVQFN32 DESCRIPTION plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm plastic, heatsink very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm - - - - - - - 27 27 39 31 40 69 6 MIN. - - - - - - - TYP. UDA1380 MAX. - - - - - - - UNIT Headphone driver (supply voltage 3.0 V) Po(rms) output power (RMS value) 35 -60 -82 -24 90 60 68 mW dB dB dB dB dB dB (THD+N)/S48 total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz S/N48 cs signal-to-noise ratio at fs = 48 kHz channel separation - 74 - dB - - - - - - - mW mW mW mW mW mW W VERSION SOT487-1 SOT617-1 2002 Sep 16 7 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 6 BLOCK DIAGRAM UDA1380 handbook, full pagewidth VDDA(AD) 32 (28) VSSA(AD) 30 (26) PGA VADCP VADCN 2 (30) SDC VREF 29 (25) PGA VDDD 6 (2) VDDA(DA) 26 (22) 1 (29) VINR 4 (32) VINL 31 (27) SDC +29 dB 3 (31) VINM MIC AMP SDC n.c. ADC ADC UDA1380TT (UDA1380HN) 5 (1) RESET DECIMATION FILTER AGC 13 (9) SYSCLK DC-CANCELLATION FILTER DATAO BCKO WSO BCKI WSI DATAI 9 (5) 7 (3) 8 (4) 10 (6) 11 (7) 12 (8) DATA OUTPUT INTERFACE 17 (13) L3 or I2C-BUS INTERFACE 16 (12) 18 (14) 19 (15) L3CLOCK/SCL L3MODE L3DATA/SDA SEL_L3_IIC DATA INPUT INTERFACE DSP FEATURES 15 (11) RTCB WSPLL INTERPOLATION FILTER NOISE SHAPER ANA VC VOUTL 27 (23) HEADPHONE DRIVER 23 (19) VOUTLHP FSDAC FSDAC ANA VC 25 (21) HEADPHONE DRIVER VOUTR 24 (20) 22 (18) 20 (16) 21 (17) 28 (24) 14 (10) MGU526 VREF(HP) VOUTRHP VSSA(DA) VSSD VDDA(HP) VSSA(HP) Pin numbers for UDA1380HN in parentheses. Fig.1 Block diagram. 2002 Sep 16 8 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 7 PINNING PIN SYMBOL UDA1380TT UDA1380HN VINR VADCN VINM VADCP RESET 1 2 3 4 5 29 30 31 32 1 analog pad analog pad analog pad analog pad 5 V tolerant digital input pad; push-pull; TTL with hysteresis; pull-down digital supply pad 5 V tolerant digital bidirectional pad; push-pull input; 3-state output; 5 ns slew-rate control; TTL with hysteresis output pad; push-pull; 5 ns slew-rate control; CMOS 5 V tolerant digital input pad; push-pull; TTL with hysteresis TYPE UDA1380 DESCRIPTION ADC input right, also connected to the mixer input of the FSDAC ADC reference voltage microphone input ADC reference voltage pin RESET with pull-down, for making Power-On Reset (POR) digital supply voltage bit clock output word select output VDDD BCKO WSO 6 7 8 2 3 4 DATAO BCKI WSI DATAI SYSCLK VSSD RTCB 9 10 11 12 13 14 15 5 6 7 8 9 10 11 data output bit clock input word select input data input system clock 256fs, 384fs, 512fs or 768fs input digital ground pad 5 V tolerant digital input pad; push-pull; TTL with hysteresis; pull-down 5 V tolerant digital bidirectional pad; push-pull input; 3-state output; 5 ns slew-rate control; TTL with hysteresis 5 V tolerant digital input pad; push-pull; TTL with hysteresis I2C-bus pad; 400 kHz I2C-bus specification 5 V tolerant digital input pad; push-pull; TTL with hysteresis analog ground pad analog pad analog pad analog pad analog supply pad analog pad analog supply pad analog pad 9 digital ground test control input, to be connected to digital ground in the application L3-bus mode input or pin A1 for I2C-bus slave address setting L3MODE 16 12 L3CLOCK/SCL L3DATA/SDA SEL_L3_IIC VSSA(HP) VOUTRHP VREF(HP) VOUTLHP VDDA(HP) VOUTR VDDA(DA) VOUTL 2002 Sep 16 17 18 19 20 21 22 23 24 25 26 27 13 14 15 16 17 18 19 20 21 22 23 L3-bus or I2C-bus clock input L3-bus or I2C-bus data input and output input channel select headphone ground headphone output right headphone reference voltage headphone output left headphone supply voltage DAC output right DAC analog supply voltage DAC output left Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 PIN SYMBOL UDA1380TT UDA1380HN VSSA(DA) VREF VSSA(AD) VINL VDDA(AD) 28 29 30 31 32 24 25 26 27 28 analog ground pad analog pad analog ground pad analog pad analog supply pad TYPE UDA1380 DESCRIPTION DAC analog ground ADC and DAC reference voltage ADC analog ground ADC input left, also connected to the mixer input of the FSDAC ADC analog supply voltage handbook, halfpage VINR VADCN VINM VADCP RESET VDDD BCKO WSO DATAO 1 2 3 4 5 6 7 8 32 VDDA(AD) 13 L3CLOCK/SCL 31 VINL 12 L3MODE SYSCLK 30 VSSA(AD) 29 VREF 28 VSSA(DA) 27 VOUTL 26 VDDA(DA) 25 VOUTR DATAI WSI BCKI 8 7 6 5 4 3 2 1 handbook, halfpage 14 L3DATA/SDA 15 SEL_L3_IIC 16 VSSA(HP) 17 VOUTRHP 18 VREF(HP) 19 VOUTLHP 20 VDDA(HP) 21 VOUTR 22 VDDA(DA) 23 VOUTL 24 VSSA(DA) 10 VSSD VINM 31 UDA1380TT 9 24 VDDA(HP) 23 VOUTLHP 22 VREF(HP) 21 VOUTRHP 20 VSSA(HP) 19 SEL_L3_IIC 18 L3DATA/SDA 17 L3CLOCK/SCL MGU525 DATAO WSO BCKO VDDD RESET UDA1380HN BCKI 10 WSI 11 DATAI 12 SYSCLK 13 VSSD 14 RTCB 15 L3MODE 16 VADCP 32 VADCN 30 11 RTCB 9 VINR 29 VDDA(AD) 28 VINL 27 VSSA(AD) 26 VREF 25 MGW778 Fig.2 Pin configuration UDA1380TT. Fig.3 Pin configuration UDA1380HN. 2002 Sep 16 10 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8 8.1 FUNCTIONAL DESCRIPTION Clock modes 8.1.1 WSPLL REQUIREMENTS UDA1380 There are two clock systems: * A SYSCLK signal, coming from the system or the SSA1 chip * A WSPLL which generates the internal clocks from the incoming WSI signal. The system frequency applied to pin SYSCLK is selectable. The options are 256fs, 384fs, 512fs and 768fs. The system clock must be locked in frequency to the digital interface signals. Remark: Since there is neither a fixed reference clock available in the IC itself, nor a fixed clock available in the system the IC is in, there is no auto sample rate conversion detection circuitry. The system can run in several modes, using the two clock systems: * Both the DAC and the ADC part can run at the applied SYSCLK input. In this case the WSPLL is powered-down * The ADC can run at the SYSCLK input, and at the same time the DAC part can run (at a different frequency) at the clock re-generated from the WSI signal * The ADC and the DAC can both run at the clock regenerated from the WSI signal. The WSPLL is meant to lock onto the WSI input signal, and regenerates a 256fs and 128fs signal for the FSDAC and the interpolator core (and for the decimator if needed). Since the operating range of the WSPLL is from 75 to 150 MHz, the complete range of 8 to 100 kHz sampling frequency must be divided into smaller parts, as given in Table 1, using Fig.4 as a reference. This means that the user must set the input range of the WSI input signal. In case the SYSCLK is used for clocking the complete system (decimator including interpolator) the WSPLL must be powered-down with bit ADC_CLK via the L3-bus or I2C-bus. The SEL_LOOP_DIV[1:0] can be controlled by the PLL1 and PLL0 bits in the L3-bus or I2C-bus register. handbook, halfpage WSI VCO DIV1 PRE1 128fs (digital parts) 256fs (ADC and FSDAC) MGU527 Fig.4 WSPLL set-up. Table 1 WSPLL divider settings SEL_LOOP_DIV[1:0] 00 01 10 11 PRE1 8 4 2 2 DIV1 1536 1536 1536 768 76 to 153 VCO FREQUENCY (MHz) WORD SELECT FREQUENCY (kHz) 6.25 to 12.5 12.5 to 25 25 to 50 50 to 100 2002 Sep 16 11 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8.1.2 CLOCK DISTRIBUTION UDA1380 Figure 5 shows the main clock distribution for the SYSCLK domain and the WSPLL clock domain. For power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the L3-bus and I2C-bus registers (ADC_CLK). The DAC part of the UDA1380 can operate from 8 to 100 kHz sampling frequency (fs). This applies to the DAC part only; the ADC part can run from 8 to 55 kHz. handbook, full pagewidth enable clock 256/384/512/768fs ADC_CLK SYSCLK CLK_DIV 128fs 128fs ADC DECIMATOR L3 or I2C-BUS REGISTER DECIMATOR I2S-BUS OUTPUT BLOCK I2S-BUS INPUT BLOCK L3 or I2C-BUS REGISTER INTERPOLATOR INTERPOLATOR enable clock enable clock 256fs WSI WSPLL 128fs DAC_CLK 128fs FSDAC enable clock MGU528 Fig.5 Clock routing for the main blocks inside the coder-decoder. 2002 Sep 16 12 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8.2 ADC analog front-end 8.2.1 UDA1380 APPLICATIONS AND POWER-DOWN MODES The analog front-end of the UDA1380 consists of one stereo ADC with a selector in front of it (see Fig.6). Using this selector one can either select the microphone input with the microphone amplifier (LNA) with a fixed 29 dB gain and VGA (no PGA, since a real microphone amplifier is much better with respect to noise), or the line input which has a PGA for having 0 or 6 dB gain (for supporting 1 and 2 V (RMS) input). The PGA also provides gain control from 0 to 24 dB in steps of 3 dB. Remarks: * The input impedance of the PGA (line input) is 12 k, for the LNA this is 5 k * The LNA is standard equipped with a microphone power supply. Since this normally requires two extra pins, this feature will not be used inside the UDA1380. Instead, the microphone supply block is replaced by the VGA block. The following Power-down modes and functional modes are supported: * Power-down mode in which the power consumption is very low (only leakage currents) In this mode there is no reference voltage at the line input * Line input mode, in which the PGA can be used * Microphone mode, in which the rest of the non-used PGAs and ADCs are powered-down * Mixed PGA and LNA mode: one line input and one microphone input. More information on the analog frond-end is given in Section 8.11.1. handbook, full pagewidth SEL_MIC VINR 1 (29) PGA SDC ADC bitstream right VINL 31 (27) PGA SDC ADC bitstream left VINM 3 (31) LNA SDC MGU530 Pin numbers for UDA1380HN in parentheses. Fig.6 Analog front-end. 8.2.2 LNA WITH VGA 8.2.3 APPLICATIONS WITH 2 V (RMS) INPUT The LNA is equipped with a VGA. The function of the VGA is to have additional variable analog gain from 0 to 30 dB in steps of 2 dB. This provides more flexibility in the choice of the microphone. For the line input it is preferable to have 0 dB and 6 dB gain settings in order to be able to apply both 1 and 2 V (RMS) input signals, using a series resistance. For this purpose a PGA is used which has 0 to 24 dB gain, in steps of 3 dB. 2002 Sep 16 13 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 In applications in which a 2 V (RMS) input signal is used, a 12 k resistor must be used in series with the input of the ADC (see Fig.7). This forms a voltage divider together with the internal ADC resistor and ensures that the voltage, applied to the input of the IC, never exceeds 1 V (RMS). Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is applied to the ADC in the same application, the gain switch must be set to 6 dB. An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 2; the power supply voltage is assumed to be 3 V. Table 3 UDA1380 Decimation filter characteristics CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs at 0 dB input analog VALUE (dB) 0.01 -70 >135 -1.5 ITEM Pass-band ripple Stop band Dynamic range Digital output level 8.3.1 OVERLOAD DETECTION The UDA1380 is equipped with an overload detector which can be read out from the L3-bus or I2C-bus interface. In practice the output is used to indicate whenever the output data, in either the output of the left or right channel, exceeds -1 dB (the actual figure is -1.16 dB) of the maximum possible digital swing. When this condition is detected the output bit OVERFLOW in the L3-bus register is forced to logic 1 for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. 8.3.2 VOLUME CONTROL handbook, halfpage external resistor VINL, 31, 12 k 12 k VINR 1 input signal 2 V (RMS) (27, VREF 29) PGA VDDA = 3 V MGU529 Pin numbers for UDA1380HN in parentheses. Fig.7 ADC front-end with PGA (line input). The decimator is equipped with a digital volume control. This volume control is separate for left and right and can be set with bits ML_DEC [7:0] and bits MR_DEC [7:0] via the L3-bus or I2C-bus interface. The range is from +24 dB to -63.5 dB and mutes in steps of 0.5 dB. 8.3.3 MUTE Table 2 Application modes using input gain stage INPUT GAIN SWITCH 0 dB 6 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE 2 V (RMS) 1 V (RMS) 1 V (RMS) 0.5 V (RMS) RESISTOR (12 k) Present Absent The decimator is equipped with a dB-linear mute which mutes the signal in 256 steps of 0.5 dB. 8.3.4 AGC FUNCTION The decimation filter is equipped with an AGC block. This function is intended, when enabled, to keep the output signal at a constant level. The AGC can be used for microphone applications in which the distance to the microphone is not always the same. The AGC can be enabled via an L3-bus or I2C-bus bit by setting the bit to logic 1. In that case it bypasses the digital volume control. Via the L3-bus or I2C-bus interface also some other settings of the AGC, like the attack and decay settings and the target level settings, can be made. Remark: The DC filter before the decimation filter must be enabled by setting the L3-bus or I2C-bus bit SKIP_DCFIL to logic 0 when AGC is in operation; otherwise the output will be disturbed by the DC offset added in the ADC. 8.3 Decimation filter (ADC) The decimation from 128fs is performed in two stages. The sin x first stage realizes a ---------- characteristic with a decimation x factor of 16. The second stage consists of 3 half-band filters, each decimating by a factor 2. The filter characteristics are shown in Table 3. 2002 Sep 16 14 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8.4 Interpolation filter (DAC) 8.4.2 SOUND FEATURES UDA1380 The interpolation digital filter interpolates from 1 to 64fs or to 128fs, by cascading FIR filters, see Table 4. The interpolator is equipped with several sound features like volume control, mute, de-emphasis and tone control. Table 4 Interpolation filter characteristics ITEM Pass-band ripple Stop band Dynamic range 8.4.1 DIGITAL MUTE In addition, there are basic sound features: * dB-linear volume control using 14-bit coefficients in steps of 0.25 dB: range 0 to -78 dB maximum suppression and - dB: applies to both master volume and mixing volume control * De-emphasis for 32, 44.1, 48 and 96 kHz for both channel 1 and 2 (selectable independently) * Treble, which is selectable gain for high frequencies (positive gain only), the edge frequency of the treble is fixed (depends on the sampling frequency). Can be set for left and right independently: - Two settings: fc = 1.5 kHz and fc = 3 kHz, assuming sampling frequency is 44.1 kHz - Both settings have 0 to 6 dB gain range in steps of 2 dB * Bass boost, which is selectable gain for low frequencies (positive gain only). The edge frequency of the bass boost is fixed and depends on the sampling frequency. Can be set for left and right independently: - Two settings: fc = 250 Hz and fc = 300 Hz, assuming sampling frequency is 44.1 kHz - First setting: 0 to 18 dB gain range in steps of 2 dB - Second setting: 0 to 24 dB gain range in steps of 2 dB. 8.5 Noise shaper CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.025 -60 >135 Muting the DAC will result in a cosine roll-off soft mute, using 4 x 32 = 128 samples in normal mode (or 3 ms at 44.1 kHz sampling frequency). The cosine roll-off curve is illustrated in Fig.8. These cosine roll-off functions are implemented for both the digital mixer and the master mute inside the DAC data path, see Section 8.8. handbook, halfpage 1 MGU119 mute factor 0.8 0.6 The noise shaper consists of two mono 3rd-order noise shapers and one time-multiplexed stereo 5th-order noise shaper. The order of the noise shaper can be chosen between 3rd-order (which runs at 128fs) and 5th-order (which runs at 64fs) via bit SEL_NS in the L3-bus or I2C-bus register. The preferable choice for the noise shaper order is: * 3rd-order noise shaper is preferred at low sampling frequencies, for instance between 8 and 32 kHz. This is for preventing out-of-band noise from the noise shaper to move into the audio band * 5th-order noise shaper is normally used at higher sampling frequencies, normally from 32 to 100 kHz. The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using an FSDAC. 0.4 0.2 0 0 5 10 15 20 t (ms) 25 Fig.8 Mute as a function of raised cosine roll-off, displayed assuming 44.1 kHz. 2002 Sep 16 15 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8.6 8.6.1 FSDAC GENERAL INFORMATION 8.7 Headphone driver UDA1380 The Filter-Stream Digital-to-Analog Converter (FSDAC) is a semi-digital reconstruction filter that converts the 1-bit data stream (running at either 64fs for the 5th-order noise shaper or 128fs for the 3rd-order noise shaper) of the noise shaper into an analog output voltage. The filter coefficients are implemented as current sources, and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity are achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal, capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage. Remark: When the FSDAC is powered-down, the output of the FSDAC becomes high impedance. 8.6.2 ANALOG MIXER INPUT The UDA1380 is equipped with a headphone driver which can deliver 36 mW (at 3.0 V power supply) into a 16 load. The headphone driver does not need external DC decoupling capacitors because it can be DC coupled with respect to a special headphone output reference voltage. This saves two external capacitors (which is quite useful in a portable device). The headphone driver is equipped with short-circuit protection on all three operational amplifiers (left, right and the virtual ground). Each of the operational amplifiers has a signalling bit which becomes logic 1 in case the limiter is activated, for instance in case of a short-circuit. This means the microcontroller in the system can poll the L3-bus or I2C-bus register of the headphone driver and as soon as, and for as long as, the short-circuit detection bits are activated, the microcontroller can signal the user that something is wrong or power-down the headphone driver (for instance, for energy-saving purposes). Remark: To improve headphone channel separation performance, the distance between VREF(HP) and the micro speaker port must be minimized. 8.8 8.8.1 Digital and analog mixers (DAC) DIGITAL MIXER The FSDAC has a mixer input, which makes it possible to mix an analog signal to the output signal of the FSDAC itself. In schematic form this is given in Fig.9. This mixer input can be used for instance for mixing-in a GSM signal or an FM signal directly to the line output. In the UDA1380, the mixer input is connected from the ADC line input via an AVC unit. Remark: Before the AVC unit can be used stand-alone, meaning without the digital part running, first the DAC part must be initialised in order to have the DAC output generating zero current. Otherwise the signal will be clipped. The ADC output signal and digital input signal can be mixed without external DSP as shown in Fig.10. This mixer can be controlled via the microcontroller interface, and must only be enabled when the ADC and the DAC are running at the same frequency. In addition, the mixer output signal can also be applied to the I2S-bus output interface. handbook, halfpage to analog mixer input bitstream FSDAC MGU531 Fig.9 Mixing signals to the FSDAC output (analog domain). 2002 Sep 16 16 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 handbook, data from full pagewidth decimation filter (channel 2) DE-EMPHASIS VOLUME AND MUTE 1fs mixing before sound features BASS-BOOST AND TREBLE mixing after sound features master to interpolation filter MGU532 from digital data input (channel 1) DE-EMPHASIS VOLUME AND MUTE 2fs VOLUME INTERPOLATION AND FILTER MUTE SEL_SOURCE I2S-BUS OUTPUT BLOCK Fig.10 Digital mixer (DAC). 8.8.2 ANALOG MIXER The analog mixer, which uses the mixer input of the FSDAC, can mix a signal into the FSDAC output signal via an AVC unit (see Fig.11). The mixer can be used to mix a signal into the FSDAC output signal and play it via the headphone driver without the complete coder-decoder running. The analog control range is 0 to -64.5 dB and mutes in steps of 1.5 dB, with a gain of 16.5 dB (so actually the range is from +16.5 dB to -48 dB plus mute). PON_AVC handbook, full pagewidth from analog front-end RESISTOR NETWORK to FSDAC mixer input AVC[5:0] L3 or I2C-bus control bits enable mixer (EN_AVC) MGU533 Fig.11 Analog mixer configuration. 2002 Sep 16 17 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8.9 Application modes 8.11 Power-down requirements UDA1380 The operation mode can be set with pin SEL_L3_IIC, either to L3-bus mode (LOW) or to the I2C-bus mode (HIGH) as given in Table 5. For all features in microcontroller mode see Chapter 9. Table 5 Pin function in the selected mode PIN L3CLOCK/SCL L3MODE L3DATA/SDA L3-BUS MODE SEL_L3_IIC = L L3CLOCK L3MODE L3DATA MODE SEL_L3_IIC = H SCL A1 SDA I2C-BUS The following blocks have power-down control via the L3-bus or I2C-bus interface: * Microphone amplifier (LNA) including its Single-Ended to Differential Converter (SDC) and VGA * ADC plus SDC and the PGA, for left and right separate * Bias generation circuit for the front-end and the FSDAC * Headphone driver * WSPLL * FSDAC. Clocks of the decimator, interpolator and the analog blocks have separate enable and disable controls. Remark: In the I2C-bus mode there is a bit A1 which sets the LSB bit of the address of the UDA1380. In L3-bus mode this bit is not available, meaning the device has only one L3-bus device address. 8.10 Power-on reset The UDA1380 has a dedicated pin RESET, which has a pull-down resistor. This way a Power-on reset circuit can be made with a capacitor and a resistor at the pin. The internal pull-down resistor cannot be used because of the 5 V tolerant nature of the pad. The pull-down resistor is shielded from the outside world by a transmission gate in order to support 5 V tolerance. The reset timing is determined by the external capacitor and resistor which are connected to the pin RESET, and the internal pull-down resistor. By the Power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the L3-bus and I2C-bus control modes. Remark: The reset time should be at least 1 s, and during the reset time the system clock should be running. In case the WSPLL is selected as the clock source, a clock must be connected to the SYSCLK input in order to have proper reset of the L3-bus or I2C-bus registers. This is because by default the clock source is set to SYSCLK. 2002 Sep 16 18 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8.11.1 ANALOG FRONT-END UDA1380 Figure 12 shows the power control inside the analog front-end. The control of all power-on pins of the ADC front-end is done via separate L3-bus or I2C-bus bits. handbook, full pagewidth PGA_GAINCTRLL PGA_GAINCTRLR VINR 1 (29) PGA SDC ADC bitstream right VINL 31 (27) PGA SDC ADC bitstream left VINM 3 (31) LNA SDC PON_BIAS PON_LNA PON_PGAR PON_ADCR PON_ADCL FE BIAS MGU534 PON_PGAL VREF Pin numbers for UDA1380HN in parentheses. Fig.12 Analog front-end power-down. 8.11.2 FSDAC POWER CONTROL The FSDAC block has power-on pins: one of which shuts down the DAC itself, but leaves the output still at VREF voltage (which is half the power supply). This function is set by the bit PON_DAC in the L3-bus or I2C-bus register. A second L3-bus or I2C-bus bit shuts down the complete bias circuit of the FSDAC, via bit PON_BIAS in the L3-bus or I2C-bus register. This bit PON_BIAS acts the same as given in Fig.12 for the analog front-end. 8.12 Plop prevention the FSDAC or headphone driver can be powered-down. In case the FSDAC or headphone driver must be powered-up, first the analog part is switched on, then the digital part is demuted * When the ADC must be powered-down, a digital mute sequence must be applied. When the digital output signal is completely muted, the ADC can be powered-down. In case the ADC must be powered-up, first the analog part must be powered-up, then the digital part must be demuted * When there is a change of for example clock divider settings or clock source (selecting between SYSCLK and WSPLL clock), then also digital mute for that block (either decimator or interpolator) should be used. Remark: All items mentioned in Section 8.12 are not `hard-wired' implemented, but to be followed by the users as a guideline for plop prevention. Plops are ticks and other strange sounds, that can occur when a part of a device is powered-up or powered-down, or when switching between modes is done. Some ways to prevent plops from occurring are: * When the FSDAC or headphone driver must be powered-down, first a digital mute is applied. After that 2002 Sep 16 19 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 8.13 Digital audio data input and output UDA1380 The slave and master modes can be selected by the bit Serial Interface Mode (SIM) in the L3-bus or I2C-bus interface. 9 L3-BUS INTERFACE DESCRIPTION The supported audio formats for the control modes are: * I2S-bus * MSB-justified * LSB-justified, 16 bits * LSB-justified, 18 bits * LSB-justified, 20 bits * LSB-justified, 24 bits (only for the output interface). The bit clock BCK can be up to 128fs, or in other words the BCK frequency is 128 times the WS frequency or less: fBCK 128fWS Remark: The WS edge must coincide with the negative edge of the BCK at all times, for proper operation of the digital I/O data interface. Figure 13 shows the interface signals. 8.13.1 DIGITAL AUDIO INPUT INTERFACE The UDA1380 has an L3-bus microcontroller interface mode. Controllable system and digital sound processing features are: * Software reset * System clock frequency (selection between 256fs, 384fs, 512fs and 768fs clock divider settings) * Clock mode setting, for instance, which block runs at which clock, and clock enabling * Power control for the WSPLL * Data input and data output format control, for input and output independently including data source selection for the digital output interface * ADC features: - Digital mute - AGC enable and settings - Polarity control - Input line amplifier control (0 to 24 dB in steps of 3 dB) - DC filtering control - Digital gain control (+24 to -63 dB gain in steps of 0.5 dB) for left and right - Power control - VGA of the microphone input - Selection of line or microphone input * DAC and headphone driver features: - Power control FSDAC and headphone driver - Polarity control - Mixing control (only available when both decimator and interpolator run at the same speed). This includes the mixer volumes, mute and mixer position switch - De-emphasis control - Master volume and balance control - Flat/minimum/maximum settings for the bass boost and treble - Tone control: bass boost and treble - Master mute control - Headphone driver short-circuit protection status bits. The digital audio input interface is slave only, meaning the system must provide the WSI and BCKI signals (next to the DATAI signal). Either the WSPLL locks onto the WSI signal and provides the internal clocks for the interpolator and the FSDAC, or a system clock must be applied which must be in frequency lock to the digital data input interface signals. 8.13.2 DIGITAL AUDIO OUTPUT INTERFACE The digital audio output interface can be either master or slave. The data source for the data output can be selected from either the decimator (ADC front-end) or the digital mixer output. Remark: The digital mixer output is only valid if both the decimator and the interpolator run at the same clock: * In slave mode the signals on pins BCKO, WSO and SYSCLK must be applied from the application (signals must be in frequency lock) and the UDA1380 returns the DATAO signal from the decimator. The applied signal from pin BCKO can be for instance: 32fs, 48fs, 64fs, 96fs or 128fs * In master mode the SYSCLK signal must be applied from the system, but the UDA1380 returns with the BCKO, WSO and the DATAO signals. For the BCKO clock, there are 2 general rules: - When the SYSCLK is either 256fs or 512fs, the BCKO frequency is supposed to be 64fs - When the SYSCLK is either 384fs or 768fs, the BCKO signal should be 48fs. 2002 Sep 16 20 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ndbook, full pagewidth 2002 Sep 16 21 Philips Semiconductors Stereo audio coder-decoder for MD, CD and MP3 WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 MSB I2S-BUS FORMAT WS 1 BCK 2 LEFT 3 >=8 1 2 RIGHT 3 >=8 DATA MSB B2 LSB MSB B2 LSB MSB B2 MSB-JUSTIFIED FORMAT WS LEFT 16 BCK 15 2 1 RIGHT 16 15 2 1 DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS MSB B2 B15 LSB WS LEFT 18 17 16 15 2 1 RIGHT 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B17 LSB LSB-JUSTIFIED FORMAT 18 BITS MSB B2 B3 B4 B17 LSB WS LEFT 20 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 Product specification UDA1380 DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB MBL121 Fig.13 Serial interface input and output formats. Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 9.1 Introduction UDA1380 The device address consists of one byte, which is split-up in two parts: * Bits 7 to 2 represent a 6-bit device address. In the UDA1380 this is 000001 * Bits 1 to 0 called Data Operation Mode, or DOM bits, represent the type of data transfer according to Table 6. 9.3 Slave address The exchange of data and control information between the microcontroller and the UDA1380, is accomplished through a serial hardware interface comprising the following pins: L3DATA/SDA: microcontroller interface data line L3MODE: microcontroller interface mode line L3CLOCK/SCL: microcontroller interface clock line. Information transfer via the microcontroller bus is organized LSB first, and in accordance with the so called `L3' format, in which two different modes of operation can be distinguished: address mode and data transfer mode. Inside the microcontroller there is a hand-shake mechanism which takes care of proper data transfer from the microcontroller clock, to the destination clock domains. This means that when data is sent to the microcontroller interface, the system clock must be running. 9.2 Device addressing The UDA1380 acts as a slave receiver or a slave transmitter. Therefore the signals L3CLOCK and L3MODE are only input signals. The data signal L3DATA is a bidirectional line. The UDA1380 slave address is shown in Table 7. Table 7 (MSB) 0 9.4 0 0 L3 slave address BIT 0 0 (LSB) 1 Register addressing The device addressing mode is used to select a device for subsequent data transfer. The address mode is characterized by the signal on pin L3MODE being LOW and a burst of 8 pulses on pin L3CLOCK/SCL, accompanied by 8 bits. The fundamental timing is shown in Figs 14 and 15. Basically, two types of transfer can be defined: data transfer to the device, and data transfer from the device, as given in Table 6. Table 6 DOM BIT 1 0 0 1 1 Selection of data transfer DOM BIT 0 0 1 0 1 not used not used DATA and STATUS write or pre-read DATA and STATUS read TRANSFER After sending the device address, including the flags (the DOM bits) whether information is read or written, one byte is sent with the destination register address using 7 bits, and one bit which signals whether information will be read or written. The fundamental timing for L3 is given in Fig.19. Basically there are three forms for register addressing: * Register addressing for L3 write: the first bit is a logic 0 indicating a write action to the destination register, followed by seven register address bits * Prepare read addressing: the first bit of the byte is logic 1; signalling data will be read from the register indicated * The read action itself: in this case the device returns a register address prior to sending data from that register. When the first bit of the byte is logic 0, the register address was valid, in case the first bit is a logic 1 the register address was invalid. Remarks: * Each time a new destination address needs to be written, the device address must be sent again * When addressing the device for the first time after power-up of the device, at least one L3 clock-cycle must be given to enable the L3 interface. Table 6 shows that there are two types of data transfers: DATA and STATUS which can be read and written. Table 6 also shows that the DATA and STATUS read and write actions are combined. 2002 Sep 16 22 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 9.5 Data write mode UDA1380 For writing data to a device, four bytes must be sent. Figure 14 explains the data write mode in a signal diagram: * One byte with the device address, being `00000110', which is including the LSB code 01 for signalling write to the device * One byte starting with a logic 0 for signalling write, followed by 7 bits indicating the destination address * Two data bytes. The SYSCLK signal must be applied in data write mode. Table 8 L3 write data BIT L3 MODE Addressing mode Data transfer 1 Data transfer 2 Data transfer 3 Notes 1. First bit in time. 2. Last bit in time. 9.6 Data read mode * One byte with the device address including `11' is sent to the device, being 00000111. The `11' indicates that the device must write data to the microcontroller, then the microcontroller frees the L3DATA-bus so the UDA1380 can send the register address byte and its two-byte contents * The device now writes the requested register address on the bus, indicating whether the requested register was valid or not (logic 0 means valid, logic 1 means invalid) * The device writes the data from the requested register on the bus, being two bytes. The SYSCLK signal must be applied in data read mode. DATA TYPE device address register address MS data byte LS data byte 0(1) 0 0 D15 D7 1 1 A6 D14 D6 2 1 A5 D13 D5 3 0 A4 D12 D4 4 0 A3 D11 D3 5 0 A2 D10 D2 6 0 A1 D9 D1 7(2) 0 A0 D8 D0 For reading from the device, first a prepare-read must be done. After this, the device address is sent again. The device then returns with the register address, indicating whether the address was valid or not, and the data of the register. The following five steps explain this procedure, and an example of transmission is given in Fig.15. * One byte with the device address, being `00000110', which is including the LSB code 01 for signalling write to the address * One byte is sent with the register address from which it needs to be read. This byte starts with a logic 1, which indicates that there will be a read action from the register 2002 Sep 16 23 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 Table 9 L3 prepare read data BIT L3 MODE Addressing mode Data transfer 1 Notes 1. First bit in time. 2. Last bit in time. Table 10 L3 read data BIT L3 MODE Addressing mode Data transfer 1; note 3 Data transfer 2; note 3 Data transfer 3; note 3 Notes 1. First bit in time. 2. Last bit in time. 3. Data transfer from the UDA1380 to the microcontroller. DATA TYPE device address register address MS data byte LS data byte 0(1) 1 0: valid 1: invalid D15 D7 1 1 A6 D14 D6 2 1 A5 D13 D5 3 0 A4 D12 D4 4 0 A3 D11 D3 5 0 A2 D10 D2 DATA TYPE device address register address 0(1) 0 1 1 1 A6 2 1 A5 3 0 A4 4 0 A3 5 0 A2 UDA1380 6 0 A1 7(2) 0 A0 6 0 A1 D9 D1 7(2) 0 A0 D8 D0 2002 Sep 16 24 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Sep 16 L3CLOCK L3MODE device address L3DATA 0 1 0 MGU535 Philips Semiconductors Stereo audio coder-decoder for MD, CD and MP3 register address data byte 1 data byte 2 DOM bits write Fig.14 Data write mode for L3 version 2. 25 L3CLOCK L3MODE device address L3DATA 01 DOM bits 1 read prepare read register address 11 device address 0/1 register address data byte 1 data byte 2 Product specification valid/non-valid UDA1380 send by the device MGU536 Fig.15 Data read mode for L3 version 2. Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 10 I2C-BUS INTERFACE DESCRIPTION The UDA1380 supports I2C-bus microcontroller interface mode as well as the L3-bus mode; all features can be controlled by the microcontroller with the same register addresses as in the L3-bus mode. The exchange of data and control information between the microcontroller and the UDA1380 in I2C-bus mode is accomplished through a serial hardware interface comprising the following pins: L3CLOCK/SCL: microcontroller interface clock line, SCL L3MODE: sets the bit A1of the I2C-bus device address L3DATA/SDA: microcontroller interface data line, SDA. Figure 20 shows the clock and data timing of the I2C-bus transfer. 10.1 Addressing Table 12 I2C-bus register address (MSB) 0 A6 A5 BIT A4 A3 10.1.1 DEVICE ADDRESS (PIN A1) UDA1380 The UDA1380 acts as either a slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. Table 11 shows the device address of the UDA1380. The device can be set to one of the two addresses by using bit A1 (which is pin L3MODE) to select. Table 11 I2C-bus device address (MSB) 0 10.1.2 0 1 1 BIT 0 A1 0 (LSB) R/W REGISTER ADDRESS Table 12 shows the register address format of the UDA1380. The register mapping in I2C-bus mode is the same as for the L3-bus interface. Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The UDA1380 device address is [A6 to A0] 00110(A1)0, with bit A1 as the address selection bit (two addresses possible). (LSB) A2 A1 A0 2002 Sep 16 26 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10.2 WRITE cycle 2002 Sep 16 27 Philips Semiconductors Stereo audio coder-decoder for MD, CD and MP3 Table 13 shows the I2C-bus configuration for a WRITE cycle. The WRITE cycle is used to write the data to the internal registers. The device and register addresses are one byte each, the setting data is always a pair of two bytes. The format of the WRITE cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `00110A10' and a logic 0 (WRITE) for the bit R/W. 3. This is followed by an acknowledge (A) by the UDA1380. 4. After this the microcontroller writes the register address (ADDR) (8 bits) where the writing of the register content of the UDA1380 must start. 5. The UDA1380 acknowledges this register address (A). 6. The UDA1380 sends the two-bytes data with the Most Significant (MS) byte first, and then the Least Significant (LS) byte, each time acknowledged by the microcontroller. 7. The UDA1380 stops this cycle by generating an acknowledge (A). 8. Finally, the UDA1380 frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 13 Master transmitter writes to UDA1380 registers in the I2C-bus mode INITIAL BYTE START S DEVICE ADDRESS 00110A10 R/W 0 A REGISTER ADDRESS ADDR A MS data byte MS1 A ACKNOWLEDGE FROM UDA1380 LS data byte LS1 A ... A ... A MSn A LSn A STOP P auto increment if repeated n groups of 2 bytes are transmitted Product specification UDA1380 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 10.3 READ cycle 2002 Sep 16 28 S Philips Semiconductors Stereo audio coder-decoder for MD, CD and MP3 Table 14 shows the I2C-bus configuration for a READ cycle. The READ cycle is used to read the data values from the internal registers. The format of the READ cycle is as follows: 1. The microcontroller starts with a start condition (S). 2. The first byte (8 bits) contains the device address `00110A10' and a logic 0 (WRITE) for the bit R/W. 3. This is followed by an acknowledge (A) by the UDA1380. 4. After this the microcontroller writes the register address (ADDR) where the reading of the register content of the UDA1380 must start. 5. The UDA1380 acknowledges this register address. 6. Then the microcontroller generates a repeated start (Sr). 7. Then the microcontroller generates the device address `00110A10' again, but this time followed by a logic 1 (READ) of the bit R/W. 8. The UDA1380 sends the two-bytes register contents with the Most Significant (MS) byte first, and then the Least Significant (LS) byte, each time acknowledged by the microcontroller. 9. The microcontroller stops this cycle by generating a negative acknowledge (NA). 10. Finally, the UDA1380 frees the I2C-bus and the microcontroller can generate a stop condition (P). Table 14 Master transmitter reads from the UDA1380 registers in the I2C-bus mode INITIAL BYTE DEVICE ADDRESS 00110A10 R/W 0 A ADDR A Sr ACKNOWLEDGE FROM UDA1380 REGISTER ADDRESS 00110A10 R/W 1 A MS data byte MS1 A ACKNOWLEDGE FROM MICROCONTROLLER LS data byte LS1 A ... A ... A MSn A LSn NA P auto increment if repeated n groups of 2 bytes are transmitted Product specification UDA1380 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11 REGISTER MAPPING Table 15 Register map of control settings (write) REGISTER ADDRESS FUNCTION UDA1380 System settings (running at the L3-bus or I2C-bus clock itself) 00H 01H 02H 03H 04H evaluation modes, WSPLL settings, clock divider and clock selectors I2S-bus I/O settings power control settings analog mixer settings reserved Interpolation filter (running at 128fs interpolator clock) 10H 11H 12H 13H 14H master volume control mixer volume control mode selection, left and right bass boost, and treble settings master mute, channel 1 and channel 2 de-emphasis and channel mute mixer, silence detector and interpolation filter oversampling settings Decimator (running at 128fs decimator clock) 20H 21H 22H 23H Software reset 7FH restore L3-default values decimator volume control PGA settings and mute ADC settings AGC settings Table 16 Register map of status bits (read-out) REGISTER ADDRESS Headphone driver and interpolation filter 18H Decimator 28H decimator status interpolation filter status FUNCTION 2002 Sep 16 29 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.1 Evaluation modes and clock settings UDA1380 Table 17 Register address 00H BIT Symbol Default BIT Symbol Default 15 EV2 0 7 - 0 14 EV1 0 6 - 0 13 EV0 0 5 ADC_CLK 0 12 - 0 4 DAC_CLK 0 11 EN_ADC 0 3 sys_div1 0 10 EN_DEC 1 2 sys_div0 0 9 EN_DAC 0 1 PLL1 1 8 EN_INT 1 0 PLL0 0 Table 18 Description of register bits BIT 15 to 13 SYMBOL EV[2:0] DESCRIPTION Evaluation bits. Bits EV2, EV1 and EV0 are special control bits for manufacturer's evaluation and must always be kept at their default values for normal operation of UDA1380; default value 000, see Table 17. default value 0 ADC clock enable. A 1-bit value to enable the system clock (from SYSCLK input) to the analog part of the ADC. See Fig.5 for more detailed information. When this bit is logic 0: clock to ADC disabled and when this bit is logic 1: clock to ADC running. Default value 0. Decimator clock enable. A 1-bit value to enable the 128fs clock to the decimator, the 128fs part of the I2S-bus output block and the clock to the ADC L3-bus or I2C-bus registers. See Fig.5 for more detailed information. When this bit is logic 0: clock to the decimator disabled. When this bit is logic 1: clock to the decimator running. Default value 1. FSDAC clock enable. A 1-bit value to enable the 256fs clock to the analog part of the FSDAC. See Fig.5 for more detailed information. When this bit is logic 0: clock to FSDAC disabled. When this bit is logic 1: clock to the FSDAC running. Default value 0. Interpolator clock enable. A 1-bit value to enable the 128fs clock to the interpolator, the 128fs part of the I2S-bus input block and the interpolator registers of the L3-bus or I2C-bus interface. See Fig.5 for more detailed information. When this bit is logic 0: clock to the interpolator disabled. When this bit is logic 1: clock to the interpolator running. Default value 1. default value 00 ADC clock select. A 1-bit value to select the 128fs clock and the clock of the analog part for the decimator and the ADC. This can either be the clock derived from the SYSCLK input or from the WSPLL. When this bit is logic 0: SYSCLK is used. When this bit is logic 1: WSPLL is used. Default value 0. 12 11 - EN_ADC 10 EN_DEC 9 EN_DAC 8 EN_INT 7 and 6 5 - ADC_CLK 2002 Sep 16 30 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 BIT 4 SYMBOL DAC_CLK DESCRIPTION UDA1380 DAC clock select. A 1-bit signal to select the clocks for the DAC (interpolator and FSDAC analog block). In both cases the clocks must be 128fs and 256fs (for the analog part), but in one case the clock is derived from the WSI clock, and in the other case the clock is derived from the SYSCLK. When this bit is logic 0: SYSCLK is used. When this bit is logic 1: WSPLL is used. Default value 0. Dividers for system clock input. A 2-bit value to select the proper division factor for the SYSCLK input in such a way that a128fs clock will be generated from the SYSCLK clock signal. The 128fs clock is needed for clocking the decimator and interpolator. Default value 00, see Table 19. WSPLL setting. A 2-bit value to select the WSPLL input frequency range. These set the proper divider setting for the WSPLL. The input is the WSI signal, the output inside the IC is a 128fs and a 256fs clock. Default value 10, see Table 20. 3 and 2 sys_div[1:0] 1 and 0 PLL[1:0] Table 19 Dividers for system clock input sys_div1 0 0 1 1 Table 20 WSPLL settings PLL1 0 0 1 1 PLL0 0 1 0 1 INPUT FREQUENCY RANGE (kHz) ON PIN WSI 6.25 to 12.5 12.5 to 25 25 to 50 (default) 50 to 100 sys_div0 0 1 0 1 INPUT CLOCK ON PIN SYSCLK 256fs (default) 384fs 512fs 768fs 2002 Sep 16 31 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.2 I2S-bus input and output settings UDA1380 Table 21 Register address 01H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 - 0 6 SEL_ SOURCE 0 13 - 0 5 - 0 12 - 0 4 SIM 0 11 - 0 3 - 0 10 SFORI2 0 2 SFORO2 0 9 SFORI1 0 1 SFORO1 0 8 SFORI0 0 0 SFORO0 0 Table 22 Description of register bits BIT 15 to 11 10 to 8 7 6 - SFORI[2:0] - SEL_SOURCE SYMBOL default value 00000 Digital data input formats. A 3-bit value to select the digital input data format (DATAI input). Default value 000, see Table 23. default value 0 Digital output interface mode settings. A 1-bit value SEL_SOURCE to set the mode of the digital output interface source to either the decimator output or the digital mixer output. When this bit is logic 0: source digital output interface mode, set to decimator. When this bit is logic 1: source digital output interface mode, set to digital mixer output. Default value 0. default value 0 Digital output interface mode settings. A 1-bit value SIM sets the mode of the digital output interface. The speed of the BCKO pad, being 64fs or 48fs, is selected by the bits sys_div[1:0]. In case the 384fs or 768fs mode is selected the output clock is 48fs, in case 256fs or 512fs is selected, the BCKO is 64fs. When this bit is logic 0: mode of digital output interface is set to slave. When this bit is logic 1: mode of digital output interface is set to master. Default value 0. default value 0 Digital data output formats. A 3-bit value to set the digital data output format (on pin DATAO). Default value 000, see Table 24. DESCRIPTION 5 4 - SIM 3 2 to 0 - SFORO[2:0] Table 23 Digital data input formats SFORI2 0 0 0 0 1 1 1 1 2002 Sep 16 SFORI1 0 0 1 1 0 0 1 1 SFORI0 0 1 0 1 1 0 0 1 32 SERIAL_FORMAT_DAI I2S-bus (default) LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits MSB-justified not used: mapped to I2S-bus Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 Table 24 Digital data output formats SFORO2 0 0 0 0 1 1 1 1 11.3 11.3.1 SFORO1 0 0 1 1 0 0 1 1 Power control settings POWER CONTROL SETTING BIAS CIRCUITS SFORO0 0 1 0 1 0 1 0 1 SERIAL_FORMAT_DAO I2S-bus (default) LSB-justified, 16 bits LSB-justified, 18 bits LSB-justified, 20 bits LSB-justified, 24 bits MSB-justified not used: mapped to I2S-bus UDA1380 Using a 1-bit value, the power control settings of the bias circuits of the ADC, AVC and FSDAC can be set. When this bit is set to logic 0, the complete bias circuits of the analog front-end and the FSDAC are shut down. In this case, the reference voltage disappears from the input of the ADCs and LNA and the output of the FSDAC, this can cause plops, but saves power. Table 25 Register address 02H BIT Symbol Default BIT Symbol Default 15 PON_PLL 0 7 EN_AVC 0 14 - 0 6 PON_AVC 0 13 PON_HP 0 5 - 0 12 - 0 4 PON_LNA 0 11 - 0 3 PON_ PGAL 0 10 PON_DAC 0 2 PON_ ADCL 0 9 - 0 1 PON_ PGAR 0 8 PON_ BIAS 0 0 PON_ ADCR 0 Table 26 Description of register bits BIT 15 14 13 SYMBOL PON_PLL - PON_HP DESCRIPTION Power-on WSPLL. When this bit is logic 0: power-off; when this bit is logic 1: power-on. Default value 0. default value 0 Power-on headphone driver. A 1-bit value to switch the headphone driver into power-on or Power-down mode. When this bit is logic 0: headphone driver is powered-off; when this bit is logic 1: headphone driver is powered-on. Default value 0. default value 00 Power-on DAC. A 1-bit value to switch the DAC into power-on or Power-down mode. In this Power-down mode the VREF (half the power supply voltage) will remain on the FSDAC output. When this bit is logic 0: DAC is powered-off; when this bit is logic 1: DAC is powered-on. Default value 0. default value 0 33 12 and 11 10 - PON_DAC 9 2002 Sep 16 - Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 BIT 8 SYMBOL PON_BIAS DESCRIPTION UDA1380 Power-on BIAS. A 1-bit value to set the power control setting of the ADC, AVC and FSDAC. When this bit is logic 0: ADC, AVC and FSDAC bias circuits are powered-off; when this bit is logic 1: Power-on bias for ADC, AVC and FSDAC. Default value 0. Enable control AVC. A 1-bit value to enable or disable the analog mixer. When this bit is logic 0: analog mixer is disabled; when this bit is logic 1: analog mixer is enabled. Default value 0. Power-on AVC. A 1-bit value to have power-on control for the analog mixer. When this bit is logic 0: analog mixer powered-off; when this bit is logic 1: analog mixer powered-on. Default value 0. default value 0 Power-on LNA. A 1-bit value to power-on the LNA and SDC. When this bit is logic 0: LNA and SDC are powered-off; when this bit is logic 1: LNA and SDC are powered-on. Default value 0. Power-on PGAL. A 1-bit value to have power-on control for the PGA left. When this bit is logic 0: left PGA is powered-off; when this bit is logic 1: left PGA is powered-on. Default value 0. Power-on ADCL. A 1-bit value to have power-on control for the ADC left. When this bit is logic 0: left ADC is powered-off; when this bit is logic 1: left ADC is powered-on. Default value 0. Power-on PGAR. A 1-bit value to have power-on control for the PGA right. When this bit is logic 0: right PGA is powered-off; when this bit is logic 1: right PGA is powered-on. Default value 0. Power-on ADCR. A 1-bit value to have power-on control for the ADC right. When this bit is logic 0: right ADC is powered-off; when this bit is logic 1: right ADC is powered-on. Default value 0. 7 EN_AVC 6 PON_AVC 5 4 - PON_LNA 3 PON_PGAL 2 PON_ADCL 1 PON_PGAR 0 PON_ADCR 2002 Sep 16 34 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.4 Analog mixer settings UDA1380 Table 27 Register address 03H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 - 0 6 - 0 13 AVCL5 1 5 AVCR5 1 12 AVCL4 1 4 AVCR4 1 11 AVCL3 1 3 AVCR3 1 10 AVCL2 1 2 AVCR2 1 9 AVCL1 1 1 AVCR1 1 8 AVCL0 1 0 AVCR0 1 Table 28 Description of register bits BIT 15 and 14 13 to 8 - AVCL[5:0] SYMBOL default value 00 Analog volume control. A 6-bit value to program the left master volume attenuation. The range is from +16.5 to -48 and - dB in steps of 1.5 dB. The 16.5 dB gain is there to boost the 150 mV (RMS) which comes from for instance an FM tuner IC to 1 V (RMS) needed to drive the headphone driver full-swing. Default value 111111, see Table 29. default value 00 Analog volume control. A 6-bit value to program the right master volume attenuation. The range is from +16.5 to -48 and - dB in steps of 1.5 dB. The 16.5 dB gain is there to boost the 150 mV (RMS) which comes from for instance an FM tuner IC to 1 V (RMS) needed to drive the headphone driver full-swing. Default value 111111, see Table 29. DESCRIPTION 7 and 6 5 to 0 - AVCR[5:0] 2002 Sep 16 35 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 Table 29 Analog volume control AVCL5 AVCR5 0 0 0 0 0 : 1 1 : 1 11.5 AVCL4 AVCR4 0 0 0 0 0 : 0 0 : 1 Reserved AVCL3 AVCR3 0 0 0 0 0 : 1 1 : 1 AVCL2 AVCR2 0 0 0 0 1 : 0 1 : 1 AVCL1 AVCR1 0 0 1 1 0 : 1 0 : 1 AVCL0 AVCR0 0 1 0 1 0 : 1 0 : 1 UDA1380 VOLUME (dB) 16.5 15 13.5 12 10.5 : -48 - : - (default) Bits RSV12, RSV11, RSV10, RSV02, RSV01, and RSV00 are special control bits for manufacturer's evaluation and must always be kept at their default values for normal operation of UDA1380. Table 30 Register address 04H BIT Symbol Default BIT Symbol Default 15 - - 7 - - 14 - - 6 - - 13 - - 5 - - 12 - - 4 - - 11 - - 3 - - 10 RSV12 0 2 RSV02 0 9 RSV11 1 1 RSV01 1 8 RSV10 0 0 RSV00 0 Table 31 Description of the register bits BIT 15 to 11 10 9 8 7 to 3 2 1 0 SYMBOL - RSV12 RSV11 RSV10 - RSV02 RSV01 RSV00 not used Reserved bit. Default value 0 Reserved bit. Default value 1 Reserved bit. Default value 0 not used Reserved bit. Default value 0 Reserved bit. Default value 1 Reserved bit. Default value 0 DESCRIPTION 2002 Sep 16 36 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.6 Master volume control UDA1380 Table 32 Register address 10H BIT Symbol Default BIT Symbol Default 15 MVCR_7 0 7 MVCL_7 0 14 MVCR_6 0 6 MVCL_6 0 13 MVCR_5 0 5 MVCL_5 0 12 MVCR_4 0 4 MVCL_4 0 11 MVCR_3 0 3 MVCL_3 0 10 MVCR_2 0 2 MVCL_2 0 9 MVCR_1 0 1 MVCL_1 0 8 MVCR_0 0 0 MVCL_0 0 Table 33 Description of the register bits BIT 15 to 8 SYMBOL MVCR_[7:0] DESCRIPTION Master volume control right. An 8-bit value to program the right channel volume attenuation. The range is from 0 to -78 dB and - dB in steps of 0.25 dB. Default value 00000000, see Table 34. Master volume control left. An 8-bit value to program the left channel volume attenuation. The range is from 0 to -78 dB and - dB in steps of 0.25 dB. Default value 00000000, see Table 34. 7 to 0 MVCL_[7:0] Table 34 Master volume control bits MVCR_7 MVCL_7 0 0 0 0 0 : 1 1 1 1 1 1 1 1 : 1 1 1 1 1 MVCR_6 MVCL_6 0 0 0 0 0 : 1 1 1 1 1 1 1 1 : 1 1 1 1 1 MVCR_5 MVCL_5 0 0 0 0 0 : 0 0 0 0 0 0 0 0 : 1 1 1 1 1 MVCR_4 MVCL_4 0 0 0 0 0 : 0 0 0 0 0 1 1 1 : 0 1 1 1 1 MVCR_3 MVCL_3 0 0 0 0 0 : 1 1 1 1 1 0 0 1 : 1 0 0 1 1 MVCR_2 MVCL_2 0 0 0 0 1 : 0 1 1 1 1 0 1 0 : 1 0 1 0 1 MVCR_1 MVCL_1 0 0 1 1 0 : 0 0 0 1 1 0 0 0 : 0 0 0 0 0 MVCR_0 MVCL_0 0 1 0 1 0 : 0 0 1 0 1 0 0 0 : 0 0 0 0 0 VOLUME (dB) 0 (default) -0.25 -0.50 -0.75 -1 : -50 -51 -51.25 -51.50 -51.75 -52 -54 -56 : -66 -69 -72 -78 - 2002 Sep 16 37 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.7 Mixer volume control UDA1380 Table 35 Register address 11H BIT Symbol Default BIT Symbol Default 15 VC2_7 1 7 VC1_7 0 14 VC2_6 1 6 VC1_6 0 13 VC2_5 1 5 VC1_5 0 12 VC2_4 1 4 VC1_4 0 11 VC2_3 1 3 VC1_3 0 10 VC2_2 1 2 VC1_2 0 9 VC2_1 1 1 VC1_1 0 8 VC2_0 1 0 VC1_0 0 Table 36 Description of the register bits BIT 15 to 8 SYMBOL VC2_[7:0] DESCRIPTION Digital mixer volume control. An 8-bit value to program the channel 2 volume attenuation. The range is 0 to -72 dB and - dB in steps of 0.25 dB. Default value for channel 2 is 00000000, see Table 37. Digital mixer volume control. An 8-bit value to program the channel 1 volume attenuation. The range is 0 to -72 dB and - dB in steps of 0.25 dB. Default value for channel 1 is 11111111, see Table 37. 7 to 0 VC1_[7:0] Table 37 Digital mixer volume control VC2_7 VC1_7 0 0 0 0 0 : 1 1 1 1 1 1 1 : 1 1 1 1 VC2_6 VC1_6 0 0 0 0 0 : 0 0 0 0 0 0 1 : 1 1 1 1 VC2_5 VC1_5 0 0 0 0 0 : 1 1 1 1 1 1 0 : 0 0 0 1 VC2_4 VC1_4 0 0 0 0 0 : 1 1 1 1 1 1 0 : 1 1 1 0 VC2_3 VC1_3 0 0 0 0 0 : 0 0 0 0 1 1 0 : 0 1 1 0 VC2_2 VC1_2 0 0 0 0 1 : 1 1 1 1 0 1 0 : 1 0 1 0 VC2_1 VC1_1 0 0 1 1 0 : 0 0 1 1 0 0 0 : 0 0 0 0 VC2_0 VC1_0 0 1 0 1 0 : 0 1 0 1 0 0 0 : 0 0 0 0 VOLUME (dB) 0 -0.25 -0.50 -0.75 -1 : -45 -45.25 -45.50 -45.75 -46 -48 -50 : -60 -63 -66 -72 2002 Sep 16 38 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 VC2_7 VC1_7 1 : 1 11.8 VC2_6 VC1_6 1 : 1 VC2_5 VC1_5 1 : 1 VC2_4 VC1_4 0 : 1 VC2_3 VC1_3 0 : 1 VC2_2 VC1_2 1 : 1 VC2_1 VC1_1 0 : 0 UDA1380 VC2_0 VC1_0 0 : 0 VOLUME (dB) - : - Mode, bass boost and treble Table 38 Register address 12H BIT Symbol Default BIT Symbol Default 15 M1 0 7 - 0 14 M0 0 6 - 0 13 TRL1 0 5 TRR1 0 12 TRL0 0 4 TRR0 0 11 BBL3 0 3 BBR3 0 10 BBL2 0 2 BBR2 0 9 BBL1 0 1 BBR1 0 8 BBL0 0 0 BBR0 0 Table 39 Description of register bits BIT 15 and 14 13 and 12 11 to 8 SYMBOL M[1:0] TRL[1:0] BBL[3:0] DESCRIPTION Flat/minimum/maximum setting. A 2-bit value to program the mode of the sound processing filters of bass boost and treble. Default value 00, see Table 40. Treble setting left. A 2-bit value to program the mode of the sound processing filter of treble. The used setting depends on the bits M1 and M0. Default value 00, see Table 41. Bass boost setting left. A 4-bit value to program the bass boost setting, which can be set for left and right independently. The used set depends on the bits M1 and M0. Default value 0000, see Table 42. default value 00 Treble setting right. A 2-bit value to program the mode of the sound processing filter of treble. Default value 00, see Table 41. Bass boost setting right. A 4-bit value to program the bass boost setting, which can be set for left and right independently. The used set depends on the mode bits. Default value 0000, see Table 42. 7 and 6 5 and 4 3 to 0 - TRR[1:0] BBR[3:0] Table 40 Flat/minimum/maximum setting bits M1 0 0 1 1 M0 0 1 0 1 MODE flat (default) minimum minimum maximum 2002 Sep 16 39 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 Table 41 Treble setting bits TRL1 TRR1 0 0 1 1 Table 42 Bass boost setting bits BBL3 BBR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BBL2 BBR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BBL1 BBR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BBL0 BBR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FLAT SET (dB) 0 (default) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MINIMUM SET (dB) 0 (default) 2 4 6 8 10 12 14 16 18 18 18 18 18 18 18 TRL0 TRR0 0 1 0 1 FLAT SET (dB) 0 (default) 0 0 0 MINIMUM SET (dB) 0 (default) 2 4 6 UDA1380 MAXIMUM SET (dB) 0 (default) 2 4 6 MAXIMUM SET (dB) 0 (default) 2 4 6 8 10 12 14 16 18 20 22 24 24 24 24 2002 Sep 16 40 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.9 Master mute, channel de-emphasis and mute UDA1380 Table 43 Register address 13H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 MTM 1 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 MT2 1 3 MT1 0 10 DE2_2 0 2 DE1_2 0 9 DE2_1 0 1 DE1_1 0 8 DE2_0 0 0 DE1_0 0 Table 44 Description of register bits BIT 15 14 - MTM SYMBOL default value 0 Master mute. A 1-bit value to enable the digital mute for the master. When this bit is logic 0: no soft mute of master. When this bit is logic 1: soft mute of master. Default value 1. default value 00 Channel 2 mute. A 1-bit value to enable the digital mute for channel 2. After enabling the mixer, bit MT2 must be set to logic 0. When this bit is logic 0: no soft mute of channel 2. When this bit is logic 1: soft mute of channel 2 (default value 1, meaning that channel 2 is always muted, even when the mixer is enabled). De-emphasis. A 3-bit value to enable the digital de-emphasis filter for channel 1 and 2. Default value 000, see Table 45. default value 0000 Channel 1 mute. A 1-bit value to enable the digital mute for channel 1. When this bit is logic 0: no soft mute of channel 1. When this bit is logic 1: soft mute of channel 1. Default value 0. De-emphasis. A 3-bit value to enable the digital de-emphasis filter for channel 1 and 2. Default value 000, see Table 45. DESCRIPTION 13 and 12 11 - MT2 10 to 8 7 to 4 3 DE2_[2:0] - MT1 2 to 0 DE1_[2:0] Table 45 De-emphasis selection bits DE2_2 DE1_2 0 0 0 0 1 DE2_1 DE1_1 0 0 1 1 0 DE2_0 DE1_0 0 1 0 1 0 FUNCTION off (default) 32 kHz 44.1 kHz 48 kHz 96 kHz 2002 Sep 16 41 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.10 Mixer, silence detector and oversampling settings Table 46 Register address 14H BIT Symbol Default BIT Symbol Default 15 DA_POL_INV 0 7 SILENCE 0 14 SEL_NS 0 6 SDET_ON 0 13 MIX_POS 0 5 SD_VALUE1 0 12 MIX 0 4 SD_VALUE0 0 11 - 0 3 - 0 10 - 0 2 - 0 UDA1380 9 - 0 1 OS1 0 8 - 0 0 OS0 0 Table 47 Description of register bits BIT 15 SYMBOL DA_POL_INV DESCRIPTION DAC polarity control. A 1-bit value to control the signal polarity of the DAC output signal. When this bit is logic 0: DAC output not inverted. When this bit is logic 1: DAC output inverted. Default value 0. Noise shaper order select. A 1-bit value to select between the 3rd-order and the 5th-order noise shaper. When this bit is logic 0: select 3rd-order noise shaper. When this bit is logic 1: select 5th-order noise shaper. Default value 0. Mixer signal control. A 2-bit value to select the digital mixer settings inside the interpolation filter. Default value 0. Default the mixer is off, see Table 48. default value 0000 Silence detector. A 1-bit value to force the DAC output to silence. When this bit is logic 0: no overruling. The setting of the FSDAC silence switch depends on the status of the digital silence detector circuit and the master_mute status. When this bit is logic 1: overruling. The FSDAC silence switch is activated, independent of the status of the digital silence detector circuit or the master_mute status. Default value 0. Silence detector enable. A 1-bit value to enable the digital silence detector. When this bit is logic 0: silence detection circuit disabled. When this bit is logic 1: silence detection circuit enabled. Default value 0. Silence detector settings. A 2-bit value to program the silence detector, the number of `ZERO' samples counted before the silence detector signals whether there has been digital silence. Default value 00, see Table 49. default value 00 Oversampling input settings. A 2-bit value to select the oversampling input mode. Default value 00, see Table 50. 14 SEL_NS 13 12 11 to 8 7 MIX_POS MIX - SILENCE 6 SDET_ON 5 and 4 SD_VALUE[1:0] 3 and 2 1 and 0 - OS[1:0] 2002 Sep 16 42 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 Table 48 Mixer signal control setting bits MIX_POS 0 1 0 MIX 0 0 1 no mixing; default FUNCTION UDA1380 volume of channel 1 is forced to 0 dB and volume of channel 2 is forced to - dB mixing is done before the sound processing: input signals are automatically scaled by 6 dB in order to prevent clipping during adding; after the addition, the 6 dB scaling is compensated mixing is done after the sound processing: input signals are automatically scaled in order to prevent clipping during adding 1 1 Table 49 Silence detector setting bits SD_VALUE1 SD_VALUE0 0 0 1 1 0 1 0 1 3200 samples; default 4800 samples 9600 samples 19200 samples FUNCTION Table 50 Oversampling input setting bits OS1 0 0 1 1 OS0 0 1 0 1 FUNCTION single-speed input is normal input; mixing possible; default double-speed input is after first half-band; no mixing possible quad-speed input is in front of noise shaper; no mixing possible reserved 11.11 Decimator volume control Table 51 Register address 20H BIT Symbol Default BIT Symbol Default 15 ML_DEC7 0 7 0 14 ML_DEC6 0 6 0 13 ML_DEC5 0 5 0 12 ML_DEC4 0 4 0 11 ML_DEC3 0 3 0 10 ML_DEC2 0 2 0 9 ML_DEC1 0 1 0 8 ML_DEC0 0 0 0 MR_DEC7 MR_DEC6 MR_DEC5 MR_DEC4 MR_DEC3 MR_DEC2 MR_DEC1 MR_DEC0 Table 52 Description of register bits BIT 15 to 8 SYMBOL ML_DEC[7:0] DESCRIPTION ADC volume control left. An 8-bit value to program the gain of the decimator for left and right independently. The ranges are +24 to -63.5 dB and - dB in steps of 0.5 dB. The default setting is 0 dB (value 00000000), see Table 53. ADC volume control right. An 8-bit value to program the gain of the decimator for left and right independently. The ranges are +24 to -63.5 dB and - dB in steps of 0.5 dB. The default setting is 0 dB (value 00000000), see Table 53. 7 to 0 MR_DEC[7:0] 2002 Sep 16 43 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 Table 53 ADC volume control setting bits UDA1380 ML_DEC7 ML_DEC6 ML_DEC5 ML_DEC4 ML_DEC3 ML_DEC2 ML_DEC1 ML_DEC0 MR_DEC7 MR_DEC6 MR_DEC5 MR_DEC4 MR_DEC3 MR_DEC2 MR_DEC1 MR_DEC0 0 0 0 : 0 0 0 1 : 1 1 1 1 1 0 0 0 : 0 0 0 1 : 0 0 0 0 0 1 1 1 : 0 0 0 1 : 0 0 0 0 0 1 0 0 : 0 0 0 1 : 0 0 0 0 0 0 1 1 : 0 0 0 1 : 0 0 0 0 0 0 1 1 : 0 0 0 1 : 1 0 0 0 0 0 1 1 : 1 0 0 1 : 0 1 1 0 0 0 1 0 : 0 1 0 1 : 0 1 0 1 0 GAIN (dB) 24 23.5 23 : 1 0.5 0 (default) -0.5 : -62 -62.5 -63 -63.5 - 11.12 PGA settings and mute Table 54 Register address 21H BIT Symbol Default BIT Symbol Default 15 MT_ADC 1 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 PGA_GAIN CTRLR3 0 3 PGA_GAIN CTRLL3 0 10 PGA_GAIN CTRLR2 0 2 PGA_GAIN CTRLL2 0 9 PGA_GAIN CTRLR1 0 1 PGA_GAIN CTRLL1 0 8 PGA_GAIN CTRLR0 0 0 PGA_GAIN CTRLL0 0 Table 55 Description of register bits BIT 15 14 to 12 SYMBOL MT_ADC - DESCRIPTION Decimator mute. A 1-bit value to enable the digital linear mute. When this bit is logic 0: no muting. When this bit is logic 1: muting. Default value 1. default value 000 2002 Sep 16 44 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 BIT 11 to 8 SYMBOL PGA_GAIN CTRLR[3:0] DESCRIPTION UDA1380 ADC input amplifier right gain settings. A 4-bit value to program the gain of the input amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB. The gain control of the PGA is independent for left and right. Default value 0000, see Table 56. default value 0 ADC input amplifier left gain settings. A 4-bit value to program the gain of the input amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB. The gain control of the PGA is independent for left and right. Default value 0000, see Table 56. 7 to 4 3 to 0 - PGA_GAIN CTRLL[3:0] Table 56 ADC input amplifier PGA gain setting bits PGA_GAINCTRLR3 PGA_GAINCTRLL3 0 0 0 0 0 0 0 0 1 11.13 ADC settings Table 57 Register address 22H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 0 4 - 0 11 0 3 SEL_LNA 0 10 0 2 SEL_MIC 0 9 VGA_CTRL1 0 1 SKIP_DCFIL 1 8 VGA_CTRL0 0 0 EN_DCFIL 0 PGA_GAINCTRLR2 PGA_GAINCTRLL2 0 0 0 0 1 1 1 1 X PGA_GAINCTRLR1 PGA_GAINCTRLL1 0 0 1 1 0 0 1 1 X PGA_GAINCTRLR0 PGA_GAINCTRLL0 0 1 0 1 0 1 0 1 X PGA_GAIN (dB) 0 (default) 3 6 9 12 15 18 21 24 ADCPOL_ INV VGA_CTRL3 VGA_CTRL2 Table 58 Description of register bits BIT 15 to 13 12 - ADCPOL_INV SYMBOL default value 000 ADC polarity control. A 1-bit value to select ADC polarity. When this bit is logic 0: polarity of ADC non-inverting. When this bit is logic 1: polarity of ADC inverting. Default value 0. DESCRIPTION 11 to 8 VGA_CTRL[3:0] Microphone input VGA gain settings. A 4-bit value to program the gain of the LNA in the microphone input channel. The range is 0 to 30 dB in steps of 2 dB. Default value 0000, see Table 59. 2002 Sep 16 45 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 BIT 7 to 4 3 - SEL_LNA SYMBOL default value 0000 DESCRIPTION UDA1380 Line input select. A 1-bit value to set the multiplexer in the analog front-end to select between the LNA or the enable-in input for the left ADC. When this bit is logic 0: select line input. When this bit is logic 1: select LNA for the left ADC. Default value 0. Microphone input select. A 1-bit value to set the multiplexer at the ADC right channel output (on bit-stream level) which selects either the right channel data or the left channel data, in case only the microphone input is used. In that case the microphone signal can be applied to the decimator for both left and right. When this bit is logic 0: select right channel ADC. When this bit is logic 1: select left channel ADC (for instance for microphone input). Default value 0. DC filter bypass. A 1-bit value set to skip the DC filter which is just before the decimator. This DC filter is there to compensate for the DC offset added in the ADC (to remove idle tones from the audio band). This DC signal added (the DC dither) must not be amplified in order to prevent clipping. Therefore this DC offset is removed first. When this bit is logic 0: DC filter enabled. When this bit is logic 1: DC filter bypassed. Default value 1. DC filter enable. A 1-bit value set to enable the DC filter which is at the output of the decimator (running at 1fs). When this bit is logic 0: DC filter disabled. When this bit is logic 1: DC filter enabled. Default value 0. 2 SEL_MIC 1 SKIP_DCFIL 0 EN_DCFIL Table 59 Microphone input VGA gain setting bits VGA_CTRL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VGA_CTRL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VGA_CTRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VGA_CTRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 LNA GAIN (dB) 0 (default) 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2002 Sep 16 46 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 11.14 AGC settings Table 60 Register address 23H BIT Symbol Default BIT Symbol Default 15 - 0 7 - 0 14 - 0 6 - 0 13 - 0 5 - 0 12 - 0 4 - 0 11 - 0 3 AGC_LEVEL1 0 10 AGC_TIME2 0 2 AGC_LEVEL0 0 9 AGC_TIME1 0 1 - 0 UDA1380 8 AGC_TIME0 0 0 AGC_EN 0 Table 61 Description of register bits BIT 15 to 11 10 to 8 - AGC_TIME[2:0] SYMBOL Default value 00000. AGC time constant settings. A 3-bit value to set the AGC time constants, being the attack and decay time constants. The given constants are for 44.1 and 8 kHz sampling frequencies, and must be scaled either down or up according to the sampling frequency used. Default value 000, see Table 62. default value 0000 AGC target level settings. A 2-bit value to set the AGC target level. Default value 00, see Table 63. default value 0 AGC enable control. A 1-bit value to enable or disable the AGC. When the AGC is enabled, the bit SKIP_DCFIL must be set to logic 0 to avoid disturbance on the output signal due to the DC offset added in the ADC. When this bit is logic 0: AGC off, manual gain control via the left and right decimator volume control. When this bit is logic 1: AGC enabled, with manual microphone gain setting via VGA. Default value 0. DESCRIPTION 7 to 4 3 and 2 1 0 - AGC_LEVEL[1:0] - AGC_EN Table 62 AGC time constant setting bits AGC SETTING AGC_TIME2 AGC_TIME1 AGC_TIME0 44.1 kHz SAMPLING ATTACK TIME (ms) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 11 16 11 16 21 11 16 21 DECAY TIME (ms) 100 100 200 200 200 400 400 400 8 kHz SAMPLING ATTACK TIME (ms) 61 88.2 61 88.2 116 61 88.2 116 DECAY TIME (ms) 551 (default) 551 1102 1102 1102 2205 2205 2205 2002 Sep 16 47 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 Table 63 AGC target level setting bits AGC_LEVEL1 0 0 1 1 AGC_LEVEL0 0 1 0 1 UDA1380 AGC TARGET LEVEL VALUE (dBFS) -5.5 (default) -8 -11.5 -14 11.15 Restore L3 default values (software reset) Table 64 Register address 7FH BIT Default value BIT Default value 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 - 10 - 2 - 9 - 1 - 8 - 0 - 11.16 Headphone driver and interpolation filter (read-out) Table 65 Register address 18H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 SDETR2 13 - 5 SDETL2 12 - 4 SDETR1 11 - 3 SDETL1 10 HP_STCTV 2 MUTE_ STATE_M 9 HP_STCTL 1 MUTE_ STATE_CH2 8 HP_STCTR 0 MUTE_ STATE_CH1 Table 66 Description of the register bits BIT 15 to 11 10 - HP_STCTV SYMBOL not used Headphone driver short-circuit detection. When this bit is logic 0: headphone driver is not short-circuit protected. When this bit is logic 1: headphone driver short-circuit protection is activated. Left headphone driver short-circuit detection. When this bit is logic 0: left channel headphone driver is not short-circuit protected. When this bit is logic 1: left channel headphone driver short-circuit protection is activated. Right headphone driver short-circuit detection. When this bit is logic 0: right channel headphone driver not short-circuit protected. When this bit is logic 1: right channel headphone driver short-circuit protection activated. not used Interpolator silence detect channel 2 right. When this bit is logic 0: interpolator on channel 2 right input has detected no silence. When this bit is logic 1: interpolator on channel 2 right input has detected silence. Interpolator silence detect channel 2 left. When this bit is logic 0: interpolator on channel 2 left input has detected no silence. When this bit is logic 1: interpolator on channel 2 left input has detected silence. 48 DESCRIPTION 9 HP_STCTL 8 HP_STCTR 7 6 - SDETR2 5 SDETL2 2002 Sep 16 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 BIT 4 SYMBOL SDETR1 DESCRIPTION UDA1380 Interpolator silence detect channel 1 right. When this bit is logic 0: interpolator on channel 1 right input has detected no silence. When this bit is logic 1: interpolator on channel 1 right input has detected silence. Interpolator silence detect channel 1 left. When this bit is logic 0: interpolator on channel 1 left input has detected no silence. When this bit is logic 1: interpolator on channel 1 left input has detected silence. Interpolator muting. A 1-bit value which signals whether the interpolator has reached mute or not. When this bit is logic 0: interpolator is not muted. When this bit is logic 1: interpolator is muted. Interpolator muting channel 2. When this bit is logic 0: interpolator channel 2 is not muted. When this bit is logic 1: interpolator channel 2 is muted. Interpolator muting channel 1. When this bit is logic 0: interpolator channel 1 is not muted. When this bit is logic 1: interpolator channel 1 is muted. 3 SDETL1 2 MUTE_STATE_M 1 0 MUTE_STATE_CH2 MUTE_STATE_CH1 11.17 Decimator read-out Table 67 Register address 28H BIT Symbol BIT Symbol 15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 AGC_STAT 11 - 3 - 10 - 2 MT_ADC_STAT 9 - 1 - 8 - 0 OVERFLOW Table 68 Description of the register bits BIT 15 to 5 4 - AGC_STAT SYMBOL not used AGC gain status. A 1-bit value which signals whether the AGC gain exceeds 8 dB or not. Only valid when the AGC is switched on. When this bit is logic 0: AGC gain <8 dB. When this bit is logic 1: AGC gain 8 dB. not used Decimator mute. A 1-bit value which signals whether the decimator has reached mute or not. When this bit is logic 0: decimator has not muted. When this bit is logic 1: decimator has muted. not used Digital output overflow detection. A 1-bit value which signals whether the digital output amplitude exceeds -1.16 dB or not. When this bit is logic 0: no overflow detected (read-out). When this bit is logic 1: overflow detected (read-out). DESCRIPTION 3 2 - MT_ADC_STAT 1 0 - OVERFLOW 2002 Sep 16 49 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal(max) Tstg Tamb Ves Ilu(prot) Isc(DAC) PARAMETER supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage latch-up protection current short-circuit current of DAC note 2 note 3 Tamb = 125 C; VDD = 3.6 V Tamb = 0 C; VDD = 3 V; note 4 output short-circuited to VSSA(DA) output short-circuited to VDDA(DA) Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 0.75 H series inductor. 4. DAC operation after short-circuiting cannot be warranted. 13 HANDLING - - 450 325 note 1 CONDITIONS - - -65 -40 -1100 -250 - MIN. 4 150 +125 +85 UDA1380 MAX. V UNIT C C C V V mA mA mA +1100 +250 200 Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is advised to take normal precautions appropriate to handling MOS devices. 14 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 85 UNIT K/W 15 QUALITY SPECIFICATION In accordance with "SNW-FQ-611D". 2002 Sep 16 50 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 16 DC CHARACTERISTICS VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL Supplies; note 1 VDDA(AD) VDDA(DA) VDDA(HP) VDDD IDDA(AD) ADC analog supply voltage DAC analog supply voltage headphone analog supply voltage digital supply voltage ADC analog supply current one ADC and microphone amplifier enabled; fs = 48 kHz two ADCs and PGA enabled; fs = 48 kHz all ADCs and PGAs power-down, but AVC activated; fs = 48 kHz all ADCs, PGAs and LNA power-down; fs = 48 kHz IDDA(DA) IDDA(HP) DAC analog supply current operating mode; fs = 48 kHz Power-down mode; fs = 48 kHz headphone analog supply current digital supply current no signal applied (quiescent current) Power-down mode IDDD operating mode; fs = 48 kHz playback mode; fs = 48 kHz record mode; fs = 48 kHz Power-down mode; fs = 48 kHz IDD(tot) total supply current playback mode (without headphone); fs = 48 kHz playback mode (with headphone); no signal; fs = 48 kHz record mode (audio); fs = 48 kHz record mode (speech); fs = 48 kHz record mode (audio and speech); fs = 48 kHz fully operating; fs = 48 kHz signal mix-in operating, using FSDAC, AVC (with headphone); no signal; fs = 48 kHz Power-down mode; fs = 48 kHz 2.4 2.4 2.4 2.4 - - - - - - - - - - - - - - - - - - - 3.0 3.0 3.0 3.0 4.5 7.0 3.3 1.0 3.4 0.1 0.9 0.1 10.0 5.0 6.0 1.0 9.0 8.8 13.0 10.0 13.0 23.0 12.0 3.6 3.6 3.6 3.6 - - - - - - - - - - - - - - - - - - - V V V V mA mA mA A mA A mA A mA mA mA A mA mA mA mA mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT - 2.0 - A 2002 Sep 16 51 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 SYMBOL PARAMETER CONDITIONS MIN. - - - - TYP. UDA1380 MAX. UNIT Digital input pins (5 V tolerant TTL compatible) VIH VIL ILI Ci VOH VOL VREF Ro(VREF) HIGH-level input voltage LOW-level input voltage input leakage current input capacitance IOH = -2 mA IOL = 2 mA with respect to VSSA(AD); note 2 2.0 -0.5 - - 5.5 +0.8 1 10 - 0.4 V V A pF Digital output pins HIGH-level output voltage LOW-level output voltage 0.85VDDD - - - V V Reference voltage reference voltage output resistance on pin VREF positive reference voltage of the ADC negative reference voltage of the ADC input resistance input capacitance 0.45VDDA 0.5VDDA - 12.5 0.55VDDA V - k Analog-to-digital converter VADCP VADCN Ri Ci RL CL - - - - 3 note 3 - - - - - - - - VDDA(AD) 0 12 24 - - - - - - - 50 - - - - - - - V V k pF Digital-to-analog converter load resistance load capacitance k pF Power consumption (supply voltage 3.0 V; fs = 48 kHz) Ptot total power dissipation playback mode (without headphone) playback mode (with headphone) record mode (audio) record mode (speech) record mode (audio and speech) full operation Power-down mode Notes 1. All supply connections must be made to the same power supply unit. 2. VDDA = VDDA(DA) = VDDA(AD). 3. When higher capacitive loads must be driven, a 100 resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. 27 27 39 31 40 69 6 mW mW mW mW mW mW W 2002 Sep 16 52 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 17 AC CHARACTERISTICS VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; fi = 1 kHz at -1 dB; Tamb = 25 C; RL = 5 k; all voltages measured with respect to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fripple = 1 kHz; Vripple = 30 mV (p-p) - TYP. -1 -1 -1 -1 -1 -1 -1 -1 -1 <0.1 -85 -85 -85 -85 -84 -83 -82 -80 -78 -37 -36 -36 -36 -35 -34 -33 -32 -30 97 100 80 MAX. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - UNIT Analog-to-digital converter Do digital output level 0 dB setting; Vi(rms) = 1.0 V 3 dB setting; Vi(rms) = 708 mV 6 dB setting; Vi(rms) = 501 mV 9 dB setting; Vi(rms) = 354 mV 12 dB setting; Vi(rms) = 252 mV 15 dB setting; Vi(rms) = 178 mV 18 dB setting; Vi(rms) = 125 mV 21 dB setting; Vi(rms) = 89 mV 24 dB setting; Vi(rms) = 63 mV Vi (THD + N)/S48 unbalance between channels at -1 dBFS total harmonic distortion-plus-noise to signal at 0 dB setting fs = 48 kHz 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting at -60 dBFS; A-weighted 0 dB setting 3 dB setting 6 dB setting 9 dB setting 12 dB setting 15 dB setting 18 dB setting 21 dB setting 24 dB setting S/N48 cs PSRR signal-to-noise ratio at fs = 48 kHz channel separation power supply rejection ratio Vi = 0 V; A-weighted dB dB dB dB dB dB dB dB dB dB dB dB dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB dB dB dB dB dB dB dB dB dB 2002 Sep 16 53 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 SYMBOL PARAMETER CONDITIONS MIN. - - - - - at 0 dBFS digital input; note 1 at 0 dB at -60 dB; A-weighted at 0 dB at -60 dB; A-weighted code = 0; A-weighted code = 0; A-weighted - - - - - - - - - fripple = 1 kHz; Vripple = 30 mV (p-p) at 0 dBFS digital input, assuming RL = 16 at 0 dB; RL = 16 at 0 dB; RL = 5 k at -60 dB; A-weighted RL = 16 using pin VREF(HP); no DC decoupling capacitors; note 2 RL = 16 single-ended application with DC decoupling capacitors (100 F typical) RL = 32 single-ended application with DC decoupling capacitors (100 F typical) S/N48 signal-to-noise ratio at fs = 48 kHz code = 0; A-weighted - TYP. - -74 -25 85 70 UDA1380 MAX. UNIT LNA input plus analog-to-digital converter Vi(rms) (THD+N)/S48 input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz signal-to-noise ratio at fs = 48 kHz channel separation at 0 dBFS digital output; 2.2 k source impedance at 0 dB at -60 dB; A-weighted Vi = 0 V; A-weighted 35 - - - - - - - - - - - - - - mV dB dB dB dB S/N48 cs Vo(rms) Vo (THD+N)/S48 Digital-to-analog converter output voltage (RMS value) unbalance between channels total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz total harmonic distortion-plus-noise to signal ratio at fs = 96 kHz signal-to-noise ratio at fs = 48 kHz signal-to-noise ratio at fs = 96 kHz channel separation power supply rejection ratio 0.9 <0.1 -88 -40 -80 -37 100 97 90 60 V dB dB dB dB dB dB dB dB dB (THD+N)/S96 S/N48 S/N96 cs PSRR Headphone driver Po(rms) (THD+N)/S48 output power (RMS value) total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz channel separation - - - - - 35 -60 -82 -24 60 - - - - - mW dB dB dB dB cs - 68 - dB - 74 - dB - 90 - dB 2002 Sep 16 54 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 SYMBOL PARAMETER CONDITIONS MIN. - at 0 dB at -60 dB; A-weighted Vi = 0 V; A-weighted - - - - TYP. UDA1380 MAX. - - - - - UNIT AVC (line input via ADC input, output on line output and headphone driver) Vi(rms) (THD+N)/S48 input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio at fs = 48 kHz signal-to-noise ratio at fs = 48 kHz channel separation 150 -80 -28 87 82 mV dB dB dB dB S/N48 cs Notes 1. The output voltage of the DAC is proportional to the DAC power supply voltage. 2. Channel separation performance is measured at the IC pin. 2002 Sep 16 55 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 18 TIMING VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 2.7 to 3.6 V; Tamb = -20 to +85 C; all voltages referenced to ground; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing; note 1 Tsys system clock cycle time fsys = 256fs fsys = 384fs fsys = 512fs fsys = 768fs tCWL tCWH system clock LOW time system clock HIGH time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz Serial interface input/output data timing (see Fig.17) fBCK Tcy(BCK) tBCKH tBCKL tr tf tsu(WS) th(WS) tsu(DATAI) th(DATAI) th(DATAO) td(DATAO-BCK) td(DATAO-WS) tr tf Tcy(CLK)L3 tCLK(L3)H tCLK(L3)L tsu(L3)A th(L3)A tsu(L3)D th(L3)D bit clock frequency bit clock cycle time bit clock HIGH time bit clock LOW time rise time fall time word select set-up time word select hold time data input set-up time data input hold time data output hold time data output to bit clock delay data output to word select delay - - 30 30 - - 10 10 10 10 0 - - note 3 note 3 note 4 note 4 note 4 - - 500 250 250 190 190 190 190 - - - - - - - - - - - - - - - - - - - - - - 128fs 1 128Tcy(s) (2) 35 23 17 17 0.3Tsys 0.4Tsys 0.3Tsys 0.4Tsys 81 54 41 27 - - - - 250 170 130 90 0.7Tsys 0.6Tsys 0.7Tsys 0.6Tsys ns ns ns ns ns ns ns ns Hz s ns ns ns ns ns ns ns ns ns ns ns - - 20 20 - - - - - 30 30 L3-bus interface timing (see Figures 18 and 19) rise time fall time L3CLOCK cycle time L3CLOCK HIGH time L3CLOCK LOW time L3MODE set-up time in address mode L3MODE hold time in address mode L3MODE set-up time in data transfer mode L3MODE hold time in data transfer mode 10 10 - - - - - - - ns/V ns/V ns ns ns ns ns ns ns 2002 Sep 16 56 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 SYMBOL tstp(L3) tsu(L3)DA th(L3)DA tsu(L3)R th(L3)R ten(L3)R tdis(L3)R PARAMETER L3MODE stop time in data transfer mode L3DATA set-up time in address and data transfer mode L3DATA hold time in address and data transfer mode L3DATA set-up time for read data L3DATA hold time for read data L3DATA enable time for read data L3DATA disable time for read data CONDITIONS MIN. 190 190 30 50 360 380 50 - - - - - - - - - - - - - - - - - - - - TYP. - - - - - - - UDA1380 MAX. UNIT ns ns ns ns ns ns ns I2C-bus interface timing; see Fig.20 fSCL tLOW tHIGH tr tf tHD;STA tSU;STA tSU;STO tBUF tSU;DAT tHD;DAT tSP Cb Notes 1. The typical value of the timing is specified at 48 kHz sampling frequency (see Fig.16). 2. Tcy(s) is the cycle time of the sample frequency. 3. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as short as possible. 4. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to 164fs cycle. 5. Cb is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF. 6. After this period, the first clock pulse is generated. 7. To be suppressed by the input filter. SCL clock frequency SCL LOW time SCL HIGH time rise time SDA and SCL fall time SDA and SCL hold time START condition set-up time repeated START set-up time STOP condition bus free time between a STOP and START condition data set-up time data hold time pulse width of spikes capacitive load for each bus line note 7 note 5 note 5 note 6 0 1.3 0.6 20 + 0.1Cb 20 + 0.1Cb 0.6 0.6 0.6 1.3 100 0 0 - 400 - - 300 300 - - - - - - 50 400 kHz s s ns ns s s s s ns s ns pF 2002 Sep 16 57 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 handbook, full pagewidth t CWH t CWL Tsys MGR984 Fig.16 Timing of system clock. handbook, full pagewidth WS t BCKH t h(WS) t su(WS) BCK t BCKL Tcy(BCK) DATAO t d(DATAO-BCK) tr tf t d(DATAO-WS) t h(DATAO) t su(DATAI) t h(DATAI) DATAI MGS756 Fig.17 Serial interface input data timing. 2002 Sep 16 58 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 handbook, full pagewidth L3MODE th(L3)A tsu(L3)A L3CLOCK tCLK(L3)L tCLK(L3)H tsu(L3)A th(L3)A Tcy(CLK)(L3) tsu(L3)DA th(L3)DA L3DATA BIT 0 BIT 7 MGL723 Fig.18 Timing of address mode. handbook, full pagewidth tstp(L3) L3MODE tCLK(L3)L tsu(L3)D tCLK(L3)H Tcy(CLK)L3 th(L3)D L3CLOCK tsu(L3)DA th(L3)DA L3DATA write BIT 0 BIT 7 L3DATA read ten(L3)R tsu(L3)R tdis(L3)R MGU015 th(L3)R Fig.19 Timing of data transfer mode for write and read. 2002 Sep 16 59 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Sep 16 SDA t BUF t LOW tr tf t HD;STA t SP Philips Semiconductors Stereo audio coder-decoder for MD, CD and MP3 Fig.20 Timing of the I2C-bus transfer. handbook, full pagewidth 60 SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr MBC611 P Product specification UDA1380 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 19 APPLICATION INFORMATION UDA1380 BLM31A601S handbook, full pagewidth +3 V BLM31A601S 100 F (16 V) VDDA VDDA VDDD 100 F (16 V) 100 F (16 V) 100 VDDA VDDD 4.7 F (16 V) ground 100 nF (63 V) 47 k 100 nF (63 V) VADCN 47 F left input (16 V) 47 F right input (16 V) microphone input 47 F (16 V) L3DATA/SDA L3CLOCK/SCL L3MODE 18 (14) 17 (13) 16 (12) VINR 2 (30) VINL 31 (27) VADCP 4 (32) 100 F (16 V) VSSA(HP) 20 (16) VDDA(HP) RESET 5 (1) (23) 27 VOUTL 47 F (16 V) 100 left output 24 (20) 10 k 1 (29) (21) 25 VOUTR 47 F (16 V) 100 right output VINM 3 (31) 10 k (5) 9 DATAO WSO BCKO UDA1380TT (UDA1380HN) (4) 8 (3) 7 SEL_L3_IIC system clock SYSCLK 47 DATAI WSI BCKI RTCB 19 (15) 13 (9) (18) 22 (19) 23 (17) 21 VOUTRHP 0 VREF 100 nF (63 V) 10 F (16 V) VREF(HP) VOUTLHP 12 (8) 11 (7) 10 (6) 15 (11) 30 (26) 32 (28) 14 (10) VSSD 6 (2) 28 (24) (25) 29 26 (22) VDDA(DA) 0 headphone VSSA(AD) VDDA(AD) VDDD VSSA(DA) MGU537 100 nF (63 V) 100 nF (63 V) 100 F (16 V) 1 VDDA 10 VDDD 100 F (16 V) 1 VDDA Pin numbers for UDA1380HN in parentheses. Fig.21 Application diagram. 2002 Sep 16 61 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 20 PACKAGE OUTLINES TSSOP32: plastic thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm UDA1380 SOT487-1 D E A X c y HE vMA Z 32 17 A2 A1 pin 1 index Lp L (A 3) A 1 e 16 bp wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.10 A1 0.15 0.05 A2 0.95 0.85 A3 0.25 bp 0.30 0.19 c 0.20 0.09 D(1) 11.10 10.90 E(2) 6.20 6.00 e 0.65 HE 8.30 7.90 L 1.00 Lp 0.75 0.50 v 0.20 w 0.10 y 0.10 Z 0.78 0.48 8 0o o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT487-1 REFERENCES IEC JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11 99-12-27 2002 Sep 16 62 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 UDA1380 HVQFN32: plastic, heatsink very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm SOT617-1 D B A terminal 1 index area A E A4 detail X e1 e 9 L 8 17 e 1/2 e C b 16 v M C A B w M C y1 C y Eh pin 1 index 1/2 e e2 1 24 32 Dh 0 2.5 scale Eh 3.25 2.95 e 0.5 e1 3.5 e2 3.5 L 0.50 0.30 v 0.2 w 0.1 y 0.05 y1 0.1 5 mm 25 X DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.00 A4 max. 0.80 b 0.35 0.18 D (1) 5.05 4.95 Dh 3.25 2.95 E (1) 5.05 4.95 Note 1. Plastic or metal protrusions of 0.076 mm maximum per side are not included. OUTLINE VERSION SOT617-1 REFERENCES IEC JEDEC MO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 01-06-07 01-08-08 2002 Sep 16 63 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 21 SOLDERING 21.1 Introduction to soldering surface mount packages UDA1380 If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 21.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 21.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 21.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2002 Sep 16 64 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 21.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3) UDA1380 SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable suitable not not recommended(4)(5) recommended(6) 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Sep 16 65 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 22 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS UDA1380 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 23 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 24 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2002 Sep 16 66 Philips Semiconductors Product specification Stereo audio coder-decoder for MD, CD and MP3 25 PURCHASE OF PHILIPS I2C COMPONENTS UDA1380 Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2002 Sep 16 67 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/02/pp68 Date of release: 2002 Sep 16 Document order number: 9397 750 09937 |
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